US4766416A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for generating the square of a function without multipliers
Assignee: General Electric Co
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Filing: 1987-07-16
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Granted: 1988-08-23
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Expires: 2007-07-16
Abstract
Abstract A pair of feedback accumulators are employed in conjunction with an oversampled analog to digital converter to generate the squared binary representation of the analog input signal. Advantage is taken of the particular form of the output waveform from oversampled analog to digital converter circuits to generate not only a standard digital output, but also the squared output after a plurality of bit-time periods L. The circuit avoids the utilization of digital multiplier circuits to perform the squaring function. The circuit is particularly applicable in the construction of electronic circuit breakers which must compute a binary representation of the square of an analog input current level signal, I 2 .
Inventors
- 👤 Sharbel E. Noujaim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:51
CPC Classifications
H; H02; H02H; H02H1/00; H02H1/0007; G; G06; G06J; G06J1/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
218 words
An analog to digital conversion circuit for producing a digital signal representative of the square of the input signal, said circuit comprising: oversampled analog to digital conversion means for producing a time sequence of a single bit output signal whose binary sum over a period of at least L bit-time periods represents, in binary form, the level of an analog input signal; a first, N-bit, clocked, feedback accumulator receiving said single bit output signal from said oversampled analog to digital conversion means and adding to said single bit signal the previous contents of said first accumulator every clock cycle; a second, clocked, feedback accumulator having 2N bits for receiving said N bit binary output signal from said first accumulator, said first accumulator output signal being supplied to N contiguous bit positions of said second accumulator beginning with the next highest bit position after the least significant bit position in said second accumulator, said second accumulator also receiving said single bit output signal in the least significant bit position of said second accumulator, said second accumulator also being configured to add to its input its previous binary output signal every bit-time clock cycle; and means for inhibiting the receipt of said N-bit binary output signal from said first accumulator, said inhibition being based upon said single bit output signal.
Claim 2
Dependent Claim
218 words
An analog to digital conversion circuit for producing a digital signal representative of the square of the input signal, said circuit comprising: oversampled analog to digital conversion means for producing a time sequence of a single bit output signal whose binary sum over a period of at least L bit-time periods represents, in binary form, the level of an analog input signal; a first, N-bit, clocked, feedback accumulator receiving said single bit output signal from said oversampled analog to digital conversion means and adding to said single bit signal the previous contents of said first accumulator every clock cycle; a second, clocked, feedback accumulator having 2N bits for receiving said N bit binary output signal from said first accumulator, said first accumulator output signal being supplied to N contiguous bit positions of said second accumulator beginning with the next highest bit position after the least significant bit position in said second accumulator, said second accumulator also receiving said single bit output signal in the least significant bit position of said second accumulator, said second accumulator also being configured to add to its input its previous binary output signal every bit-time clock cycle; and means for inhibiting the receipt of said N-bit binary output signal from said first accumulator, said inhibition being based upon said single bit output signal.
Claim 3
Dependent Claim
19 words
The circuit of claim 1 further including means to reset said accumulator to zero after each L bit-time periods.
Claim 4
Dependent Claim
23 words
The circuit of claim 1 in which said inhibiting means comprises a set of AND gates controlled by said single bit line signal.
Claim 5
Dependent Claim
191 words
A digital circuit for operating in conjunction with an oversampled analog to digital converter for producing a digital signal representative of the square of the input signal, said circuit comprising: a first, N-bit, clocked, feedback accumulator receiving a single bit output signal from an oversampled analog to digital converter and adding to said single bit signal the previous contents of said first accumulator every clock cycle; a second, clocked, feedback accumulator having 2N bits for receiving said N-bit binary output signal from said first accumulator, said first accumulator output signal being supplied to N contiguous bit positions of said second accumulator beginning with the next highest bit position after the least significant bit position of said second accumulator, said second accumulator also receiving said single bit output signal in the least significant bit position of said second accumulator, said second accumulator also being configured to add to its input its previous binary output signal every bit-time clock cycle; and means for inhibiting the receipt of said N-bit binary output signal from said first accumulator, said inhibition being based upon the single bit output signal of said oversampled analog to digital converter.
Claim 6
Dependent Claim
191 words
A digital circuit for operating in conjunction with an oversampled analog to digital converter for producing a digital signal representative of the square of the input signal, said circuit comprising: a first, N-bit, clocked, feedback accumulator receiving a single bit output signal from an oversampled analog to digital converter and adding to said single bit signal the previous contents of said first accumulator every clock cycle; a second, clocked, feedback accumulator having 2N bits for receiving said N-bit binary output signal from said first accumulator, said first accumulator output signal being supplied to N contiguous bit positions of said second accumulator beginning with the next highest bit position after the least significant bit position of said second accumulator, said second accumulator also receiving said single bit output signal in the least significant bit position of said second accumulator, said second accumulator also being configured to add to its input its previous binary output signal every bit-time clock cycle; and means for inhibiting the receipt of said N-bit binary output signal from said first accumulator, said inhibition being based upon the single bit output signal of said oversampled analog to digital converter.
Claim 7
Independent Claim
111 words
A system for generating the binary representation of the square of an analog input signal, said system comprising: an oversampled analog to digital converter for producing a time sequence of single bit signals whose binary sum over a period of at least L bit-time periods represents, in binary form, the level of an analog input signal supplied to said analog to digital converter; and a digital circuit whose input/output relationship is specified by the difference equation y(n) 2 =y(n-1) 2 +2Δ(n)y(n-1)-Δ(n) where Δ(n) is the input to said digital circuit and is also the single bit binary value of the output of said oversampled analog to digital converter at time n.
Claim 8
Independent Claim
111 words
A system for generating the binary representation of the square of an analog input signal, said system comprising: an oversampled analog to digital converter for producing a time sequence of single bit signals whose binary sum over a period of at least L bit-time periods represents, in binary form, the level of an analog input signal supplied to said analog to digital converter; and a digital circuit whose input/output relationship is specified by the difference equation y(n) 2 =y(n-1) 2 +2Δ(n)y(n-1)-Δ(n) where Δ(n) is the input to said digital circuit and is also the single bit binary value of the output of said oversampled analog to digital converter at time n.
Claim 9
Dependent Claim
72 words
The system of claim 5 in which said digital circuit includes separate digital circuits one of which exhibits an input/output relationship specified by the difference equation y(n) 2 =y(n-1) 2 +2y(n-1)+1 and the other of said separate digital circuits exhibits an input/output relation governed by the difference equation y(n) 2 =y(n-1) 2 , the one or the other of said separate digital circuits being operative depending upon whether Δ(n)=1 or Δ(n)=0, respectively.
References Cited (Backward Citations)
US4071842A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-23 | 1992-02-22 | 1992-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-23 | 1996-02-22 | 1996-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-23 | 2000-02-22 | 2000-08-23 | $7700.00 | Window Closed / Lapsed |