Circuit for preventing false programming of anti-fuse elements

Claim 1

A read only memory array, including: a plurality of two terminal anti-fuse elements, said two terminal anti-fuse elements being arranged in groups, each of said groups containing a number of said plurality of two terminal anti-fuse elements, have one terminal connected in common to a bit line, a plurality of select transistors associated with each group of two terminal anti-fuse elements, each of said plurality of select transistors having a source, a drain, and a gate, the individual ones of said plurality of select transistors associated with each group having their sources commonly connected to a source of fixed voltage, said fixed voltage selected to between about 0.5 and 2 volts above ground, each one of said plurality of select transistors having its drain connected to the second terminal of a different two terminal anti-fuse element of said group of two terminal anti-fuse elements, and each one of said plurality of select transistors having its gate connected to one of a plurality of word lines, a plurality of transistors connected in series between said bit line and an input/output line, each of said plurality of transistors having a gate coupled to a different one of a plurality of Y-select lines.