Semiconductor memory device

Claim 2

A semiconductor memory device comprising a plurality of column lines, a plurality of row lines intersecting said column lines, a plurality of programmable memory cells disposed at the intersections of said column lines and said row lines, a write terminal connectable to a write current source, the state of each of said memory cells being changed by supplying thereto an electric current larger than a predetermined value, a column selection circuit for selectively providing a first current path between a selected one of said column lines and said write terminal, a row selection circuit for selectively providing a second current path between a selected one of said row lines and a reference voltage source different from said write current source, and a current limiter circuit associated with one of said first and second current paths for limiting the amount of write current supplied to a selected memory cell designated by the selected column line and the selected row line within a regulated amount larger than said predetermined value.

Claim 3

The device according to claim 1, further comprising a voltage limiter circuit for clamping the voltage of the selected column line within a predetermined value.

Claim 4

The device according to claim 2, in which each of said memory cells is made of a bipolar transistor having an open-circuited base.

Claim 5

The device according to claim 3, in which said current limiter circuit is provided in said second current path.

Claim 6

The device according to claim 3, in which said current limiter circuit is provided in said first current path.

Claim 7

A semiconductor memory device comprising a plurality of column lines, a plurality of row lines intersecting with said column lines, a plurality of memory cells, the state of each of said memory cells being changed by supplying thereto an electric current greater than a threshold value, a write terminal to which a write power source is applied, a column node, a column selection circuit for selectively providing a first current path between said column node and a selected one of said column lines, a current limiter circuit coupled between said write terminal and said column node for limiting the amount of an electric current caused by said write power source flowing therethrough within a predetermined value more than said threshold value, said current limiter circuit including a first resistor, a first bipolar transistor having a collector coupled to said write terminal and a base coupled to said write terminal through said first resistor, a second bipolar transistor having a collector coupled to the base of said first bipolar transistor, a base coupled to an emitter of said first bipolar transistor and an emitter coupled to said column node, and a second resistor coupled between the base and the emitter of said second bipolar transistor, and a row selection circuit for selectively providing a second current path between a selected one of said row lines and a current sink source.

Claim 8

A semiconductor memory device comprising a plurality of column lines, a plurality of row lines intersecting with said column lines, a plurality of memory cells, the state of each of said memory cells being changed by supplying thereto an electric current greater than a threshold value, a write terminal to which a write power source is applied, a column node, a column selection circuit for selectively providing a first current path between said column node and a selected one of said column lines, a current limiter circuit coupled between said write terminal and said column node for limiting the amount of an electric current caused by said write power source flowing therethrough within a predetermined value more than said threshold value, said current limiter circuit including a first resistor, a first bipolar transistor having a collector coupled to said write terminal and a base coupled to said write terminal through said first resistor, a second bipolar transistor having a collector coupled to the base of said first bipolar transistor, a base coupled to an emitter of said first bipolar transistor and an emitter coupled to said column node, and a second resistor coupled between the base and the emitter of said second bipolar transistor, and a row selection circuit for selectively providing a second current path between a selected one of said row lines and a current sink source.

Claim 9

The memory device according to claim 6, curther comprising a voltage limiter circuit for clamping the voltage at the selected column line.

Claim 10

The device according to claim 7, in which each of said memory elements is made of a bipolar transistor.

Claim 11

A semiconductor device comprising a write terminal to which a write power source for writing is supplied, a plurality of row lines, a plurality of column lines intersecting with said row lines, a plurality of programmable elements arranged at intersections of said row lines and said column lines, state of each of said programmable elements being changed by passing an electric current of more than a first predetermined value therethrough, a column selection circuit for selectively electrically coupling one of said column lines to said write terminal thereby to supply a write current caused by said write power source to said one of said column lines, a common point, a row selection circuit for selectively electrically coupling one of said row lines to said common point thereby to provide an electrical path for the write current therebetween, a reference voltage source, and a current limiter circuit coupled between said common point and said reference voltage source for limiting the write current within a second predetermined value larger than said first predetermined value.

Claim 12

A semiconductor device comprising a write terminal to which a write power source for writing is supplied, a plurality of row lines, a plurality of column lines intersecting with said row lines, a plurality of programmable elements arranged at intersections of said row lines and said column lines, state of each of said programmable elements being changed by passing an electric current of more than a first predetermined value therethrough, a column selection circuit for selectively electrically coupling one of said column lines to said write terminal thereby to supply a write current caused by said write power source to said one of said column lines, a common point, a row selection circuit for selectively electrically coupling one of said row lines to said common point thereby to provide an electrical path for the write current therebetween, a reference voltage source, and a current limiter circuit coupled between said common point and said reference voltage source for limiting the write current within a second predetermined value larger than said first predetermined value.

Claim 13

The device according to claim 9, further comprising a clamp circuit for clamping a voltage at the selected column line within a preset value.

Claim 14

The device according to claim 10, in which said row selection circuit includes a plurality of NAND gates having outputs coupled to said row lines.

Claim 15

The device according to claim 11, in which said current limiter circuit includes a resistor coupled between said common point and said reference voltage and a transistor for feedbacking a voltage appeared across said resistor to one of inputs of said NAND gates.

Claim 16

A semiconductor device a comprising a write terminal to which a write power source is applied, a plurality of row lines, a plurality of column lines intersecting with said row lines, a plurality of programmable elements arranged at intersections of said row lines and column lines, a first point, a current limiter circuit coupled between said write terminal and said first point for limiting an electric current therebetween to produce a regulated amount of current at said first point, a column selection circuit for selectively electrically connecting one of said column lines to said first point, a reference voltage source, a row selection circuit for selectively coupling one of said row lines to said reference voltage source, in which said programmable element is programmed by said regulated amount of current.

Claim 17

A semiconductor device a comprising a write terminal to which a write power source is applied, a plurality of row lines, a plurality of column lines intersecting with said row lines, a plurality of programmable elements arranged at intersections of said row lines and column lines, a first point, a current limiter circuit coupled between said write terminal and said first point for limiting an electric current therebetween to produce a regulated amount of current at said first point, a column selection circuit for selectively electrically connecting one of said column lines to said first point, a reference voltage source, a row selection circuit for selectively coupling one of said row lines to said reference voltage source, in which said programmable element is programmed by said regulated amount of current.

Claim 18

The memory device according to claim 9 or 13, in which each of said programmable element is made of a bipolar transistor having a collector connected to one of said column lines and an emitter connected to one of said row lines.

Claim 19

A semiconductor memory device comprising a plurality of column lines, at least one row line intersecting with said column lines, a plurality of memory cells disposed at the intersections of said column lines and row lines, the state of each of said memory cells being changed by supplying an electric current larger than a threshold value thereto, a write terminal to which a write power source is applied, a column selection circuit for selectively providing an electric path between selected one of said column lines and said write terminal, a reference voltage source, a switching bipolar transistor, means for connecting a collector of said switching bipolar transistor to said row line, a resistor coupled between an emitter of said switching bipolar transistor and said reference voltage source, means for operatively supplying a base of said switching bipolar transistor with base current capable of conducting said switching bipolar transistor, and means for regulating the amount of said base current so as to limit the amount of current flowing through said resistor.

Claim 20

A semiconductor memory device comprising a plurality of column lines, at least one row line intersecting with said column lines, a plurality of memory cells disposed at the intersections of said column lines and row lines, the state of each of said memory cells being changed by supplying an electric current larger than a threshold value thereto, a write terminal to which a write power source is applied, a column selection circuit for selectively providing an electric path between selected one of said column lines and said write terminal, a reference voltage source, a switching bipolar transistor, means for connecting a collector of said switching bipolar transistor to said row line, a resistor coupled between an emitter of said switching bipolar transistor and said reference voltage source, means for operatively supplying a base of said switching bipolar transistor with base current capable of conducting said switching bipolar transistor, and means for regulating the amount of said base current so as to limit the amount of current flowing through said resistor.

Claim 21

The memory device according to claim 15, further comprising a clamp circuit for clamping voltage at the selected column line within a predetermined voltage.