Buffer circuitry for transferring signals from TTL circuitry to dual range CMOS circuitry

Claim 2

A buffer circuit comprising a first N channel field effect transistor comprising a source terminal connected to ground, a gate terminal connected to a source of TTL input signals, and a drain terminal; a W channel field effect transistor having a source terminal connected to the drain terminal of the N channel field effect transistor, a drain terminal connect to a source which furnishes voltage values for two operating ranges, and a gate terminal directly connected to its drain terminal whereby the W channel effect transistor remains on and saturated in both of the two operating ranges; and an inverter having an input terminal connected to the drain terminal of the N channel transistor, and an output terminal.

Claim 3

A buffer circuit comprising a first N channel field effect transistor comprising a source terminal connected to ground, a gate terminal connected to a source of TTL input signals, and a drain terminal; a W channel field effect transistor having a source terminal connected to the drain terminal of the N channel field effect transistor, a drain terminal connect to a source which furnishes voltage values for two operating ranges, and a gate terminal connected to its drain terminal; an inverter having an input terminal connected to the drain terminal of the N channel transistor, and an output terminal; and a P channel field effect transistor having its source and drain terminals connected between the source which furnishes voltage values for two operating ranges and the input of the inverter, and its gate terminal connected to an output terminal of the inverter.

Claim 4

A buffer circuit comprising a first N channel field effect transistor comprising a source terminal connected to ground, a gate terminal connected to a source of TTL input signals, and a drain terminal; a W channel field effect transistor having a source terminal connected to the drain terminal of the N channel field effect transistor, a drain terminal connect to a source which furnishes voltage values for two operating ranges, and a gate terminal connected to its drain terminal; an inverter having an input terminal connected to the drain terminal of the N channel transistor, and an output terminal; and a P channel field effect transistor having its source and drain terminals connected between the source which furnishes voltage values for two operating ranges and the input of the inverter, and its gate terminal connected to an output terminal of the inverter.

Claim 5

A buffer circuit for transferring TTL level input signals to CMOS circuitry having high and low voltage operating ranges comprising an N channel field effect transistor having gate, source, and drain terminals, the gate terminal being connected as an input terminal for the buffer circuit, the source terminal being connected to a first source of voltage at a first level, and the drain terminal being connected as an output terminal for the buffer circuit; a second source of voltage for furnishing second and third voltage levels each of which is higher than the first level; means connected between the second source of voltage and the drain terminal of the N channel field effect transistor for connecting the second source of voltage to the drain terminal of the N channel field effect transistor while maintaining the current between the second source of voltage and the drain terminal of the N channel device relatively constant whereby the N channel field effect transistor will function to switch with TTL input voltage levels when the second source of voltage furnishes either the second or the third voltage level.

Claim 6

A buffer circuit for transferring TTL level input signals to CMOS circuitry having high and low voltage operating ranges comprising an N channel field effect transistor having gate, source, and drain terminals, the gate terminal being connected as an input terminal for the buffer circuit, the source terminal being connected to a first source of voltage at a first level, and the drain terminal being connected as an output terminal for the buffer circuit; a second source of voltage for furnishing second and third voltage levels each of which is higher than the first level; means connected between the second source of voltage and the drain terminal of the N channel field effect transistor for connecting the second source of voltage to the drain terminal of the N channel field effect transistor while maintaining the current between the second source of voltage and the drain terminal of the N channel device relatively constant whereby the N channel field effect transistor will function to switch with TTL input voltage levels when the second source of voltage furnishes either the second or the third voltage level.

Claim 7

A buffer circuit as claimed in claim 3 further comprising an inverter connected to receive the output signal produced at the drain terminal of the N channel field effect transistor as an input signal.

Claim 8

A buffer circuit for transferring TTL level input signals to CMOS circuitry having high and low voltage operating ranges comprising an N channel field effect transistor having gate, source, and drain terminals, the gate terminal being connected as an input terminal for the buffer circuit, the source terminal being connected to a first source of voltage at a first level, and the drain terminal being connected as an output terminal for the buffer circuit; a second source of voltage for furnishing second and third voltage levels each of which is higher than the first level; means connected between the second source of voltage and the drain terminal of the N channel field effect transistor for connecting the second source of voltage to the drain terminal of the N channel field effect transistor while maintaining the current between the second source of voltage and the drain terminal of the N channel device relatively constant whereby the N channel field effect transistor will function to switch with TTL input voltage levels when the second source of voltage furnishes either the second or the third voltage level; an inverter connected to receive the output signal produced at the drain terminal of the N channel field effect transistor as an input signal; and a P channel field effect transistor having its source and drain terminals connected between the second source and the input of the inverter, and its gate terminal connected to an output terminal of the inverter.

Claim 9

A buffer circuit for transferring TTL level input signals to CMOS circuitry having high and low voltage operating ranges comprising an N channel field effect transistor having gate, source, and drain terminals, the gate terminal being connected as an input terminal for the buffer circuit, the source terminal being connected to a first source of voltage at a first level, and the drain terminal being connected as an output terminal for the buffer circuit; a second source of voltage for furnishing second and third voltage levels each of which is higher than the first level; means connected between the second source of voltage and the drain terminal of the N channel field effect transistor for connecting the second source of voltage to the drain terminal of the N channel field effect transistor while maintaining the current between the second source of voltage and the drain terminal of the N channel device relatively constant whereby the N channel field effect transistor will function to switch with TTL input voltage levels when the second source of voltage furnishes either the second or the third voltage level; an inverter connected to receive the output signal produced at the drain terminal of the N channel field effect transistor as an input signal; and a P channel field effect transistor having its source and drain terminals connected between the second source and the input of the inverter, and its gate terminal connected to an output terminal of the inverter.