Zero power, high impedance TTL-to-CMOS converter

Claim 1

A buffer circuit for converting a TTL input signal to a CMOS output signal, said buffer circuit drawing little or no current and presenting a high input impedance for any input signal level, said buffer circuit comprising: a source of CMOS logical one potential; a source of CMOS logical zero potential; a TTL input signal source; a source of a predetermined reference potential; first and second complementary transistor switch means having their gates connected to said TTL input signal source and their source-drain channels connected in series to said source of CMOS logical zero potential; third depletion device transistor switch means having its gate connected to said source of a predetermined reference potential and its source-drain channel connected in series between said source to CMOS logical one potential and, via the series connection of the source-drain channels of said first and second complementary switch means, said source of CMOS logical zero potential; and high input impedance inverter means for logically inverting the signal at a node in the series connection of the source-drain channels of said first and second complementary switch means between said first and second switch means, said predetermined reference potential being selected so that said third depletion device transistor switch means and the one of said first and second transistor switch means which is connected to said third depletion device transistor switch means are held off by any valid TTL logical one input signal, and so that any valid TTL logical zero input signal turns on said third depletion device transistor switch means and said one of said first and second transistor switch means.