US5036226A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal converting circuit
Assignee: Intellectual Ventures I LLC
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Filing: 1989-10-23
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Granted: 1991-07-30
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Expires: 2009-10-23
Abstract
Abstract A converter circuit for converting signals from a non-CMOS circuit into signals for a CMOS circuit. A level shifter stage in the circuit has a first MOS transistor for receiving at its gate the non-CMOS signals which always enable the first transistor and a second MOS transistor for receiving at its gate a constant voltage for enabling the second transistor. Since these transistors do not switch between non-enabling and enabling conditions in order to change the logic levels at the output of the converter circuit, the circuit operates quickly. In one embodiment the converter circuit converts ECL signals into CMOS signals, and in a second embodiment the converter circuit converts TTL signals into CMOS signals.
Inventors
- 👤 Thao T. Tonnu
- 👤 Mukesh B. Suthar
- 👤 Charles A. Kaseff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:42
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
171 words
A converter circuit for converting a first set of logic signals into a second set of logic signals, comprising: a first transistor of a first conductivity type and having first, second and control terminals, with its control terminal connected for receiving the first set of logic signals, and having its first terminal connected to a first voltage source representing a first logic level of the second set of logic signals, each of the first set of logic signals being at a voltage level sufficient to enable said first transistor; and a second transistor of a second conductivity type having first, second and control terminals, with its control terminal connected to said first voltage source and having its first terminal connected to a second voltage source representing a second logic level of the second set of logic signals, said first voltage source being sufficient to enable said second transistor; the second terminals of said first and second transistors connected to each other for providing signals representing the second set of logic signals.
Claim 2
Dependent Claim
171 words
A converter circuit for converting a first set of logic signals into a second set of logic signals, comprising: a first transistor of a first conductivity type and having first, second and control terminals, with its control terminal connected for receiving the first set of logic signals, and having its first terminal connected to a first voltage source representing a first logic level of the second set of logic signals, each of the first set of logic signals being at a voltage level sufficient to enable said first transistor; and a second transistor of a second conductivity type having first, second and control terminals, with its control terminal connected to said first voltage source and having its first terminal connected to a second voltage source representing a second logic level of the second set of logic signals, said first voltage source being sufficient to enable said second transistor; the second terminals of said first and second transistors connected to each other for providing signals representing the second set of logic signals.
Claim 3
Dependent Claim
27 words
The converter circuit of claim 1, wherein said first set of logic signals are ECL signals and wherein said second set of logic signals are CMOS signals.
Claim 4
Dependent Claim
15 words
The converter circuit of claim 2, wherein said first and second transistors are MOS transistors.
Claim 5
Dependent Claim
25 words
The converter circuit of claim 2, wherein said first transistor is an N-channel MOS transistor and wherein said second transistor is a P-channel MOS transistor.
Claim 6
Dependent Claim
29 words
The converter circuit of claim 4, wherein said first voltage source provides a "low" logic level voltage, and wherein said second voltage source provides a "high" logic level voltage.
Claim 7
Dependent Claim
162 words
A converter circuit for converting a set of ECL logic signals into a set of CMOS logic signals, comprising: a first, N-channel, MOS transistor having first, second and control terminals, having its control terminal connected for receiving said ECL logic signals, and having its first terminal connected to a voltage source providing a "low" CMOS logic level voltage, each of the ECL logic signals being at a voltage level sufficient to enable said N-channel MOS transistor; and a second, P-channel, MOS transistor having first, second and control terminals, having its control terminal connected to a voltage source for enabling said second transistor, and having its first terminal connected to a voltage source providing a "high" CMOS logic level voltage; wherein the second terminals of said first and second transistors are connected for providing the signals representing the set of CMOS logic signals; and wherein the second terminals of said first and second transistors are connected to the input of a CMOS inverter.
Claim 8
Dependent Claim
162 words
A converter circuit for converting a set of ECL logic signals into a set of CMOS logic signals, comprising: a first, N-channel, MOS transistor having first, second and control terminals, having its control terminal connected for receiving said ECL logic signals, and having its first terminal connected to a voltage source providing a "low" CMOS logic level voltage, each of the ECL logic signals being at a voltage level sufficient to enable said N-channel MOS transistor; and a second, P-channel, MOS transistor having first, second and control terminals, having its control terminal connected to a voltage source for enabling said second transistor, and having its first terminal connected to a voltage source providing a "high" CMOS logic level voltage; wherein the second terminals of said first and second transistors are connected for providing the signals representing the set of CMOS logic signals; and wherein the second terminals of said first and second transistors are connected to the input of a CMOS inverter.
Claim 9
Dependent Claim
42 words
The converter circuit of claim 6, wherein the output of said CMOS inverter is connected to the input of a second CMOS inverter, the output of said second CMOS inverter providing the full voltage levels of the second set of logic signals.
Claim 10
Dependent Claim
26 words
The converter circuit of claim 1, said first set of logic signals are TTL signals and wherein said second set of logic signals are CMOS signals.
Claim 11
Dependent Claim
15 words
The converter circuit of claim 8, wherein said first and second transistors are MOS transistors.
Claim 12
Dependent Claim
25 words
The converter circuit of claim 9, wherein said first transistor is a P-channel MOS transistor and wherein said second transistor is an N-channel MOS transistor.
Claim 13
Dependent Claim
171 words
A converter circuit for converting a first set of logic signals into a second set of logic signals, comprising: a first transistor of a first conductivity type and having a first, second and control terminals, with its control terminal connected for receiving the first set of logic signals; and a second transistor of a second conductivity type having first, second and control terminals, with its control terminal connected to a first voltage source representing a first logic level of the second set of logic signals for enabling said second transistor; the first terminal of said first transistor connected to said first voltage source and the first terminal of said second transistor connected to a second voltage source representing a second logic level of the second set of logic signals, the second terminals or said first and second transistors connected for providing a signal representing the logic levels of the second set of logic signals, with said first transistor operating in its linear region when receiving the first set of logic signals.
Claim 14
Dependent Claim
171 words
A converter circuit for converting a first set of logic signals into a second set of logic signals, comprising: a first transistor of a first conductivity type and having a first, second and control terminals, with its control terminal connected for receiving the first set of logic signals; and a second transistor of a second conductivity type having first, second and control terminals, with its control terminal connected to a first voltage source representing a first logic level of the second set of logic signals for enabling said second transistor; the first terminal of said first transistor connected to said first voltage source and the first terminal of said second transistor connected to a second voltage source representing a second logic level of the second set of logic signals, the second terminals or said first and second transistors connected for providing a signal representing the logic levels of the second set of logic signals, with said first transistor operating in its linear region when receiving the first set of logic signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-29 | 1995-01-28 | 1995-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-29 | 1999-01-28 | 1999-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-29 | 2003-01-28 | 2003-07-30 | $7700.00 | Window Closed / Lapsed |