Circuit to perform variable threshold logic

Claim 2

A high speed logic gate circuit for detecting input signals and having variable threshold capabilities comprising: a. a source of reference voltage; b. at least one first transistor means of a first gate conductivity type having the transistor source connected to reference voltage and the transistor drain connected to a common circuit point and the gate of the transistor means connected to said reference voltage or ground with at least one gate connected to said reference voltage if the first gate conductivity type is NMOS and at least one gate connected to the ground if the first gate conductivity type is PMOS to establish a predetermined circuit operating point; c. an array of parallel transistors of a second gate conductivity type, complementary to said first transistor means and having the array transistor drains connected to the common circuit point and the array transistor sources connected to the ground and gates of selected array transistors coupled for receiving signals to be monitored; and d. bi-stable inverter means having its input connected to said common circuit point so that its output changes state when the voltage at said common point exceeds a predetermined level.

Claim 3

A circuit described in claim 1 wherein the first transistor means is formed of the NMOS type transistors and the array of parallel transistors is formed of PMOS type transistors with at least one NMOS gate connected to said reference voltage.

Claim 4

A circuit as described in claim 1 wherein each transistor means of a selected complementary pair of a transistor means of a first gate conductivity type and a transistor means of a second gate conductivity type conducts similar amounts of current.

Claim 5

A circuit as described in claim 1 wherein inputs are weighted by adapting the first transistor means to include a conduction channel of a certain width being adapted to conduct an amount of current substantially similar to the amount of current passed by at least one of the transistors of the array of parallel transistors.

Claim 6

A circuit as described in claim 1 wherein inputs are weighted by adapting one or more of the transistors of the array of parallel transistors to include a conduction channel of a certain width being adapted to conduct an amount of current substantially similar to the amount of current passed by the first transistor means.

Claim 7

A high speed logic gate circuit for detecting input signals and having variable threshold capabilities comprising: a. a source of reference voltage; b. at least one first PMOS type transistor means having the transistor source connected to the reference voltage and the transistor drain connected to a common circuit point and the gate of the transistor means connected to said reference voltage or ground with at least one gate connected to ground to establish a predetermined circuit operating point; c. an array of NMOS type parallel transistors complementary to said first transistor means and having the array transistor drains connected to the common circuit point and the array transistor sources connected to ground and gates of selected array transistors coupled for receiving input signals to be monitored; and d. bi-stable inverter means having its input connected to said common circuit point so that its output changes state when the voltage at said common circuit point exceeds a predetermined level.

Claim 8

A high speed logic gate circuit for detecting input signals and having variable threshold capabilities comprising: a. a source of reference voltage; b. at least one first PMOS type transistor means having the transistor source connected to the reference voltage and the transistor drain connected to a common circuit point and the gate of the transistor means connected to said reference voltage or ground with at least one gate connected to ground to establish a predetermined circuit operating point; c. an array of NMOS type parallel transistors complementary to said first transistor means and having the array transistor drains connected to the common circuit point and the array transistor sources connected to ground and gates of selected array transistors coupled for receiving input signals to be monitored; and d. bi-stable inverter means having its input connected to said common circuit point so that its output changes state when the voltage at said common circuit point exceeds a predetermined level.

Claim 9

A high speed logic gate circuit for detecting input signals and having variable threshold capabilities comprising: a. a source of reference voltage; b. a first array of parallel transistors of a first gate conductivity type having the transistor sources connected to the reference voltage and the transistor drains connected to a common circuit point and gates of selected transistors connected to said reference voltage or ground with at least one gate connected to said reference voltage if the first gate conductivity type is NMOS and at least one gate connected to ground if the first gate conductivity type is PMOS to establish a predetermined circuit operating point; c. a second array of parallel transistors of a second gate conductivity type, complementary to said first array with one transistor for each transistor of the first array, and having the second array transistor drains connected to the common circuit point and the second transistor sources connected to ground and gates of second selected transistors coupled for receiving signals to be monitored; and d. bi-stable inverter means having its input connected to said common circuit point so that its output changes state when the voltage at said common point exceeds a predetermined level.

Claim 10

A high speed logic gate circuit for detecting input signals and having variable threshold capabilities comprising: a. a source of reference voltage; b. a first array of parallel transistors of a first gate conductivity type having the transistor sources connected to the reference voltage and the transistor drains connected to a common circuit point and gates of selected transistors connected to said reference voltage or ground with at least one gate connected to said reference voltage if the first gate conductivity type is NMOS and at least one gate connected to ground if the first gate conductivity type is PMOS to establish a predetermined circuit operating point; c. a second array of parallel transistors of a second gate conductivity type, complementary to said first array with one transistor for each transistor of the first array, and having the second array transistor drains connected to the common circuit point and the second transistor sources connected to ground and gates of second selected transistors coupled for receiving signals to be monitored; and d. bi-stable inverter means having its input connected to said common circuit point so that its output changes state when the voltage at said common point exceeds a predetermined level.

Claim 11

A circuit as described in claim 7 wherein the first array of parallel transistors is of PMOS type transistors and the second array of parallel transistors is formed of NMOS type transistors.

Claim 12

A circuit as described in claim 7 wherein gates of selected first array transistors are connected to said reference voltage and gates of non-selected first array transistors are connected to ground to determine the number of first array transistors with current flowing through them and thereby determine the threshold level.

Claim 13

A circuit as described in claim 7 wherein each transistor means of a selected complementary pair of a transistor means of a first gate conductivity type and a transistor means of a second gate conductivity type conducts similar amounts of current.

Claim 14

A circuit as described in claim 7 wherein inputs are weighted by adapting a transistor of the first transistor array to include a conduction channel of a certain width being adapted to conduct an amount of current substantially similar to the amount of current passed by one of the transistors of the second array of parallel transistors.

Claim 15

A circuit as described in claim 7 wherein inputs are weighted by adapting one or more of the transistors of the array of parallel transistors to include a conduction channel of a certain width being adapted to conduct an amount of current substantially similar to the amount of current passed by the first transistor means.

Claim 16

A high speed logic gate circuit for detecting input signals and having variable threshold capabilities comprising: a. a source of reference voltage; b. a first array of NMOS type parallel transistors having the transistor sources connected to ground and the transistor drains connected to a common circuit point and gates of selected transistors connected to said reference voltage or ground to establish a predetermined circuit operating point, with at least one gate connected to said reference voltage; c. a second array of PMOS type parallel transistors complementary to said first array with one transistor for each transistor of the first array, and having the second array transistor drains connected to the common circuit point and the second transistor sources connected to the reference voltage and gates of selected second transistors coupled for receiving signals to be monitored; and d. bi-stable inverter means having its input connected to said common circuit point so that its output changes state when the voltage at said common circuit point exceeds a predetermined level.

Claim 17

A high speed logic gate circuit for detecting input signals and having variable threshold capabilities comprising: a. a source of reference voltage; b. a first array of NMOS type parallel transistors having the transistor sources connected to ground and the transistor drains connected to a common circuit point and gates of selected transistors connected to said reference voltage or ground to establish a predetermined circuit operating point, with at least one gate connected to said reference voltage; c. a second array of PMOS type parallel transistors complementary to said first array with one transistor for each transistor of the first array, and having the second array transistor drains connected to the common circuit point and the second transistor sources connected to the reference voltage and gates of selected second transistors coupled for receiving signals to be monitored; and d. bi-stable inverter means having its input connected to said common circuit point so that its output changes state when the voltage at said common circuit point exceeds a predetermined level.