Threshold logic for integrated full adder and the like

Claim 2

A threshold logic circuit, comprising: a. a data output terminal; b. a plurality of data input terminals; c. means for producing an output at said output terminal in response to an input voltage having a predetermined relation to a predetermined threshold voltage; d. a plurality of field effect transistors connected in parallel, each of said transistors being gated by data from one of said data input terminals; e. means in series with said parallel combination of transistors and with a source of potential and cooperating with said parallel transistor combination to form a voltage divider; and f. means for applying the voltage appearing at the center tap of said voltage divider to the voltage input of said outputproducing means.

Claim 3

The logic of claim 1, in which said output-producing means is a field effect transistor inverter.

Claim 4

The logic of claim 1, in which said series means is a field effect transistor gated by said potential.

Claim 5

The logic of claim 1, in which the ''''on'''' resistances of said parallel-connected transistors are substantially equal.

Claim 6

The logic of claim 1, in which at least one of said parallel-connected transistors has an ''''on'''' resistance differing from the ''''on'''' resistance of another of said parallel-connected transistors so as to weight the input of said one transistor differently than the input of said other transistor.

Claim 7

An all-IGFET threshold logic circuit for integrated circuits, comprising: a. first and second synchronized timing pulse sources; b. a plurality of input data sources; c. an output terminal; d. a plurality of data input IGFET''s connected in parallel and gated, respectively, by said plurality of input data; e. a sampling IGFET connected in series with said parallel combination of data input IGFET''s and with said first timing pulse source; and f. an IGFET inverter including: i. a pair of parallel-connected IGFET''s connected between said second timing pulse source and said output terminal, one of said pair of IGFET''s being gated by said second timing pulse source, and the gate of the other of said pair of IGFET''s being connected to a point between said sampling IGFET and said parallel Combination of data input IGFET''s; and ii. output data storage capacitance means operatively associated with said output terminal.

Claim 8

An all-IGFET threshold logic circuit for integrated circuits, comprising: a. first and second synchronized timing pulse sources; b. a plurality of input data sources; c. an output terminal; d. a plurality of data input IGFET''s connected in parallel and gated, respectively, by said plurality of input data; e. a sampling IGFET connected in series with said parallel combination of data input IGFET''s and with said first timing pulse source; and f. an IGFET inverter including: i. a pair of parallel-connected IGFET''s connected between said second timing pulse source and said output terminal, one of said pair of IGFET''s being gated by said second timing pulse source, and the gate of the other of said pair of IGFET''s being connected to a point between said sampling IGFET and said parallel Combination of data input IGFET''s; and ii. output data storage capacitance means operatively associated with said output terminal.

Claim 9

The circuit of claim 6 wherein the ''''on'''' resistances of said plurality of parallel-connected IGFET''s are substantially equal.

Claim 10

The circuit of claim 6, in which the ''''on'''' resistances of said sampler and data input IGFET''s are so proportioned that said one of said pair of IGFET''s conducts only if fewer than a predetermined number of said data input IGFET''s conduct.

Claim 11

The circuit of claim 8, in which at least one of said data input IGFET''s has an ''''on'''' resistance substantially different from the ''''on'''' resistance of another of said data input IGFET''s so as to weight data applied thereto differently than data applied to said other data input IGFET.

Claim 12

The circuit of claim 9, in which the ''''on'''' resistances of said sampler and data input IGFET''s are so proportioned that said one of said pair of IGFET''s conducts only if the total of the weights of conducting data input IGFET''s is less than a predetermined threshold amount.

Claim 13

The circuit of claim 6, in which the ''''on'''' resistances of said sampling IGFET is so proportioned with respect to the ''''on'''' resistances of said data input IGFET''s that said first timing pulse source and said sampling IGFET represent essentially a current source.

Claim 14

The circuit of claim 6, in which said first and second timing pulse sources are ''''not-clock'''' and ''''clock'''' generators.

Claim 15

A full adder binary logic comprising a. first and second threshold gates, each including a plurality of insulated gate field effect transistors as active circuit elements; b. three addend inputs to each of said gates, a separate one of said transistors being associated with each input in each gate; c. said first gate being set to produce an output when two or more of said addend inputs are at logic ''''1''''; d. inverter means including at least one insulated gate field effect transistor for inverting the output of said first gate; e. a single fourth input to said second gate connected to the output of said inverter means and weighted at a greater weight than any of said addend inputs; and f. said second gate being set to produce an output only when the total weight of its inputs at logic ''''1'''' is greater than the weight of said fourth input alone and greater than the combined weight of any two of the other three inputs alone, whereby the output of said second gate is the sum and the output of said first gate is the carry of the binary addition of said addend inputs.

Claim 16

A full adder binary logic comprising a. first and second threshold gates, each including a plurality of insulated gate field effect transistors as active circuit elements; b. three addend inputs to each of said gates, a separate one of said transistors being associated with each input in each gate; c. said first gate being set to produce an output when two or more of said addend inputs are at logic ''''1''''; d. inverter means including at least one insulated gate field effect transistor for inverting the output of said first gate; e. a single fourth input to said second gate connected to the output of said inverter means and weighted at a greater weight than any of said addend inputs; and f. said second gate being set to produce an output only when the total weight of its inputs at logic ''''1'''' is greater than the weight of said fourth input alone and greater than the combined weight of any two of the other three inputs alone, whereby the output of said second gate is the sum and the output of said first gate is the carry of the binary addition of said addend inputs.

Claim 17

An all-IGFET binary full adder circuit for single-chip integrated logic circuits, comprising: a. first and second synchronized timing pulse sources; b. first and second threshold gates each including: i. a plurality of data input terminals; ii. an output terminal; iii. a plurality of data input IGFET''s connected in parallel and gated, respectively, by said plurality of input data; iv. a sampling IGFET connected in series with said parallel combination of data input IGFET''s and with said first timing pulse source; and v. an IGFET inverter including a pair of parallel-connected IGFET''s connected between said second timing pulse source and said output terminal, one of said pair of IGFET''s being gated by said second timing pulse source, and the gate of the other of said pair of IGFET''s being connected to a point between said sampling IGFET and said parallel combination of data input IGFET''s ; c. means for supplying addend inputs to three input terminals of each of said gates; d. said first gate being set to produce an output when two or more of said addend inputs are at logic ''''1''''; e. a fourth input to said second gate weighted at a greater weight than any of said addend inputs; f. inverteR means including i. an input terminal connected to the output terminal of said first threshold gate; ii. an output terminal connected to said fourth input terminal of said second threshold gate; and iii. a pair of parallel-connected IGFET''s connected between said second timing pulse source and said output terminal of said inverter means and gated, respectively, by said second timing pulse source and said output of said first threshold gate; g. said second gate being set to produce an output only when the total weight of its inputs at logic ''''1'''' is greater than the weight of said fourth input alone and greater than the combined weight of any two of the other three inputs alone; and h. an output data storage capacitance operatively associated with said output terminal of said second threshold gate, whereby the sum of the binary addition of said addends appears at said output terminal of said second threshold gate, and the carry of said addition appears at said output terminal of said first threshold gate.

Claim 18

An all-IGFET binary full adder circuit for single-chip integrated logic circuits, comprising: a. first and second synchronized timing pulse sources; b. first and second threshold gates each including: i. a plurality of data input terminals; ii. an output terminal; iii. a plurality of data input IGFET''s connected in parallel and gated, respectively, by said plurality of input data; iv. a sampling IGFET connected in series with said parallel combination of data input IGFET''s and with said first timing pulse source; and v. an IGFET inverter including a pair of parallel-connected IGFET''s connected between said second timing pulse source and said output terminal, one of said pair of IGFET''s being gated by said second timing pulse source, and the gate of the other of said pair of IGFET''s being connected to a point between said sampling IGFET and said parallel combination of data input IGFET''s ; c. means for supplying addend inputs to three input terminals of each of said gates; d. said first gate being set to produce an output when two or more of said addend inputs are at logic ''''1''''; e. a fourth input to said second gate weighted at a greater weight than any of said addend inputs; f. inverteR means including i. an input terminal connected to the output terminal of said first threshold gate; ii. an output terminal connected to said fourth input terminal of said second threshold gate; and iii. a pair of parallel-connected IGFET''s connected between said second timing pulse source and said output terminal of said inverter means and gated, respectively, by said second timing pulse source and said output of said first threshold gate; g. said second gate being set to produce an output only when the total weight of its inputs at logic ''''1'''' is greater than the weight of said fourth input alone and greater than the combined weight of any two of the other three inputs alone; and h. an output data storage capacitance operatively associated with said output terminal of said second threshold gate, whereby the sum of the binary addition of said addends appears at said output terminal of said second threshold gate, and the carry of said addition appears at said output terminal of said first threshold gate.

Claim 19

The circuit of claim 14, in which said first and second timing pulse sources are ''''not-clock'''' and ''''clock'''' generators.

Claim 20

The circuit of claim 14, in which the ''''on'''' resistances of said sampling IGFET''s are so proportioned with respect to the ''''on'''' resistances of said data input IGFET''s that said first timing pulse source and said sampling IGFET''s represent essentially current sources.