Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry

Claim 1

A method for providing a trench DMOS transistor cell, the method comprising the steps of: providing a substrate of semiconductor material of heavily doped first electrical conductivity type having a top surface; providing a first covering layer of semiconductor material of first electrical conductivity type having a top surface and being contiguous to and overlying the substrate top surface; providing a second covering layer of semiconductor material of second electrical conductivity type having a top surface and being contiguous to the top surface of the first covering layer and extending vertically downward from the top surface of the first covering layer into an upper portion of the first covering layer; providing a third covering layer of semiconductor material of heavily doped first electrical conductivity type having a top surface and being contiguous to and partly overlying the top surface of the second covering layer, where a portion of the second covering layer is heavily doped and this portion extends vertically upward through the third covering layer to the top surface thereof and forms an exposed pattern of the second covering layer in the top surface of the third covering layer, and where the maximum depth of the heavily doped portion of the second covering layer relative to the top surface of the third covering layer is a depth d 1 ; providing a trench having side walls and bottom walls and extending vertically downward from the top surface of the third covering layer through the third and second covering layers and through a portion of, but not all of, the first covering layer, where the trench has a maximum depth relative to the top surface of the third covering layer equal to a second depth d 2 and d 2 is less than d 1 , where the trench in horizontal cross section is approximately a polygonal stripe, and where this polygonal stripe laterally surrounds and is spaced apart from the exposed pattern of the second covering layer at the top surface of the third covering layer; providing a layer of oxide positioned within the trench and contiguous to the bottom walls and side walls of the trench so that portions, but not all, of the trench are filled with the oxide layer; providing electrically conducting semiconductor material, contiguous to the oxide layer and positioned within the trench so that the oxide layer lies between the electrically conducting semiconductor material and the bottom and side walls of the trench; and providing three electrodes that are electrically coupled to the electrically conducting semiconductor material in the trench, to the third covering layer and to the substrate, respectively, wherein the difference d 1 -d 2 of said first and second depths d 1 and d 2 is sufficient to force junction breakdown away from the trench and into the heavily doped portion of the second covering layer.

Claim 2

A method for providing a trench DMOS transistor cell, the method comprising the steps of: providing a substrate of semiconductor material of heavily doped first electrical conductivity type having a top surface; providing a first covering layer of semiconductor material of first electrical conductivity type having a top surface and being contiguous to and overlying the substrate top surface; providing a second covering layer of semiconductor material of second electrical conductivity type having a top surface and being contiguous to the top surface of the first covering layer and extending vertically downward from the top surface of the first covering layer into an upper portion of the first covering layer; providing a third covering layer of semiconductor material of heavily doped first electrical conductivity type having a top surface and being contiguous to and partly overlying the top surface of the second covering layer, where a portion of the second covering layer is heavily doped and this portion extends vertically upward through the third covering layer to the top surface thereof and forms an exposed pattern of the second covering layer in the top surface of the third covering layer, and where the maximum depth of the heavily doped portion of the second covering layer relative to the top surface of the third covering layer is a depth d 1 ; providing a trench having side walls and bottom walls and extending vertically downward from the top surface of the third covering layer through the third and second covering layers and through a portion of, but not all of, the first covering layer, where the trench has a maximum depth relative to the top surface of the third covering layer equal to a second depth d 2 and d 2 is less than d 1 , where the trench in horizontal cross section is approximately a polygonal stripe, and where this polygonal stripe laterally surrounds and is spaced apart from the exposed pattern of the second covering layer at the top surface of the third covering layer; providing a layer of oxide positioned within the trench and contiguous to the bottom walls and side walls of the trench so that portions, but not all, of the trench are filled with the oxide layer; providing electrically conducting semiconductor material, contiguous to the oxide layer and positioned within the trench so that the oxide layer lies between the electrically conducting semiconductor material and the bottom and side walls of the trench; and providing three electrodes that are electrically coupled to the electrically conducting semiconductor material in the trench, to the third covering layer and to the substrate, respectively, wherein the difference d 1 -d 2 of said first and second depths d 1 and d 2 is sufficient to force junction breakdown away from the trench and into the heavily doped portion of the second covering layer.

Claim 4

A method for providing a vertical DMOS transistor, the method comprising the steps of: providing a substrate; providing an epitaxial layer above the substrate; providing a trench in the epitaxial layer, the trench having a predetermined depth d u ; and providing a body region in the epitaxial layer, the body region having a predetermined maximum depth d max , wherein the depth d u is less than the depth d max , and wherein the difference between the depth d max and the depth d u is sufficient to force junction breakdown away from the trench and into the epitaxial layer.

Claim 5

A method for providing a vertical DMOS transistor, the method comprising the steps of: providing a substrate; providing an epitaxial layer above the substrate; providing a trench in the epitaxial layer, the trench having a predetermined depth d u ; and providing a body region in the epitaxial layer, the body region having a predetermined maximum depth d max , wherein the depth d u is less than the depth d max , and wherein the difference between the depth d max and the depth d u is sufficient to force junction breakdown away from the trench and into the epitaxial layer.

Claim 19

A method for providing a transistor, said method comprising the steps of: providing a first region of a first conductivity type; providing a second region of a second conductivity type over said first region; providing a third region of said first conductivity type such that said first and third regions are separated by said second region; providing a trench through said third and second regions; and providing a gate in said trench; wherein a portion P of said second region, which portion is spaced from said trench, extends deeper than said trench so that, if a predetermined voltage is applied to said gate and to said third region and another predetermined voltage is applied to said first region, an avalanche breakdown occurs away from a surface of said trench.

Claim 20

A method for providing a transistor, said method comprising the steps of: providing a first region of a first conductivity type; providing a second region of a second conductivity type over said first region; providing a third region of said first conductivity type such that said first and third regions are separated by said second region; providing a trench through said third and second regions; and providing a gate in said trench; wherein a portion P of said second region, which portion is spaced from said trench, extends deeper than said trench so that, if a predetermined voltage is applied to said gate and to said third region and another predetermined voltage is applied to said first region, an avalanche breakdown occurs away from a surface of said trench.

Claim 26

A method for providing a transistor, said method comprising the steps of: providing a first region of a first conductivity type; providing a second region of said first conductivity type over said first region, said second region being lighter doped than said first region; providing a third region of a second conductivity type over said second region, said second and third regions forming a junction; providing a fourth region of said first conductivity type over said third region; providing a trench through said fourth and third regions; and providing a gate in said trench; wherein a deepest part of said third region is laterally spaced from said trench; and wherein a distance between said deepest part of said third region and said first region is less than a depletion width of a planar junction which has the same doping profile as does said junction between said second and third regions at said deepest part of said third region and which is reverse biased around its breakdown voltage.

Claim 27

A method for providing a transistor, said method comprising the steps of: providing a first region of a first conductivity type; providing a second region of said first conductivity type over said first region, said second region being lighter doped than said first region; providing a third region of a second conductivity type over said second region, said second and third regions forming a junction; providing a fourth region of said first conductivity type over said third region; providing a trench through said fourth and third regions; and providing a gate in said trench; wherein a deepest part of said third region is laterally spaced from said trench; and wherein a distance between said deepest part of said third region and said first region is less than a depletion width of a planar junction which has the same doping profile as does said junction between said second and third regions at said deepest part of said third region and which is reverse biased around its breakdown voltage.