Grown side-wall silicided source/drain self-align CMOS fabrication process

Claim 1

A process for making CMOS devices comprising the steps of: preparing a wafer which includes at its front surface p-type silicon and n-type silicon regions spaced apart by field-oxide regions; depositing over the front surface a first refractory silicidable layer; implanting donor ions and acceptor ions selectively into the portions of the first layer overlying p-type regions and n-type regions, respectively; depositing a masking layer over the first layer; patterning the masking layer and the first layer to leave corresponding openings in the masking layer and the first layer for exposing portions of the p-type regions and n-type regions to serve as channels of the CMOS device; heating the wafer in an oxidizing atmosphere to form a layer of gate oxide over the exposed portions of the n-type and p-type regions, to form oxide spacers along the side walls of the openings in the first layer, and to diffuse the implanted ions out of the first layer into the underlying portions of the n-type and p-type regions to form source/drain regions of the CMOS devices with the overlying portions of the first layer serving as source/drain electrodes to such regions; depositing a polycrystalline silicon layer over the front surface of the wafer; and patterning the polycrystalline silicon layer to form gate electrodes which overlie and contact the gate oxide layer but which are electrically isolated from first layer portions by the oxide spacers and by portions of the masking layer.