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Patent US5294556A successfully refreshed from Google Patents.
US5294556A
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Method for fabricating an SOI device in alignment with a device region formed in a semiconductor substrate
Assignee: Fujitsu Ltd
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Filing: 1991-07-19
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Granted: 1994-03-15
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Expires: 2011-07-19
Abstract
Abstract A method of forming a semiconductor-on-insulator device comprises the steps of forming a first alignment mark on a semiconductor substrate at a first reference position, forming a diffusion region in the semiconductor substrate at a position defined with respect to the first alignment mark according to a predetermined relationship, providing an insulator layer on the semiconductor substrate to expose a part of an upper major surface of the semiconductor substrate, providing a semiconductor layer on the insulator layer in contact with the exposed upper major surface of the semiconductor substrate, recrystallizing the semiconductor layer by heating up to a temperature above a melting point of the semiconductor layer and cooling down subsequently below the melting point, starting from a part of the semiconductor layer in contact with the exposed upper major surface of the semiconductor substrate and moving laterally along the semiconductor layer, to form a single crystal semiconductor layer having an upper major surface formed with a depression at a second, different reference position, patterning the single crystal semiconductor layer using the depression on the upper major surface of the semiconductor layer as a second alignment mark to form a semiconductor device in alignment with the device region in the semiconductor substrate, wherein the first alignment mark at the first reference position is formed with an offset from the second reference position for the second alignment mark, the offset being chosen to cancel out an expansion of the single crystal semiconductor layer upon the step of recrystallization.
Inventors
- 👤 Seiichiro Kawamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:13
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/32; H10P14/3202; H10P14/3238; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3451; H10P14/3452; H10P14/3458; H10P14/38; H10P14/3802; H10P14/382; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1912; H10W; H10W10/00; H10W10/10; H10W10/181; H10W46/00; H10W46/201; Y; Y10; Y10S; Y10S438/00; Y10S438/975
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
361 words
A method of forming a semiconductor-on-insulator device, comprising the steps of: forming a first alignment mark on an upper major surface of a semiconductor substrate at a first reference position; forming a device region in the semiconductor substrate at a position located a selected distance from the first alignment mark, said device region including a diffusion region having an impurity element; providing an insulator layer on the upper major surface of the semiconductor substrate, said insulator layer having an upper major surface with a depression therein at the first reference position in correspondence with the first alignment mark, said insulator layer being configured so as to expose a part of the upper major surface of the semiconductor substrate; providing a semiconductor layer having corresponding first and second portions respectively on the upper major surface of the insulator layer and on, and in contact with, the exposed part of the upper major surface of the semiconductor substrate, said semiconductor layer having an upper major surface with a first depression therein at the first reference position in correspondence with the first alignment mark; recrystallizing the semiconductor layer by heating same to a first temperature, above the melting point temperature of the semiconductor layer, and cooling same subsequently to a second temperature, below the melting point temperature and less than the first temperature, starting from the second portion of the semiconductor layer in contact with the exposed part of the upper major surface of the semiconductor substrate and moving therefrom, laterally along the semiconductor layer, thereby to form a single crystal semiconductor layer having an upper major surface with a second depression therein at a second, different reference position; and patterning the single crystal semiconductor layer using the second depression in the upper major surface of the semiconductor layer as a second alignment mark and thereby to form a semiconductor device in alignment with the device region in the semiconductor substrate, the first reference position of said first alignment mark being offset from the second reference position of the second alignment mark by an amount corresponding to, and thereby cancelling out, the expansion of the single crystal semiconductor layer caused by the recrystallizing step.
Claim 2
Independent Claim
361 words
A method of forming a semiconductor-on-insulator device, comprising the steps of: forming a first alignment mark on an upper major surface of a semiconductor substrate at a first reference position; forming a device region in the semiconductor substrate at a position located a selected distance from the first alignment mark, said device region including a diffusion region having an impurity element; providing an insulator layer on the upper major surface of the semiconductor substrate, said insulator layer having an upper major surface with a depression therein at the first reference position in correspondence with the first alignment mark, said insulator layer being configured so as to expose a part of the upper major surface of the semiconductor substrate; providing a semiconductor layer having corresponding first and second portions respectively on the upper major surface of the insulator layer and on, and in contact with, the exposed part of the upper major surface of the semiconductor substrate, said semiconductor layer having an upper major surface with a first depression therein at the first reference position in correspondence with the first alignment mark; recrystallizing the semiconductor layer by heating same to a first temperature, above the melting point temperature of the semiconductor layer, and cooling same subsequently to a second temperature, below the melting point temperature and less than the first temperature, starting from the second portion of the semiconductor layer in contact with the exposed part of the upper major surface of the semiconductor substrate and moving therefrom, laterally along the semiconductor layer, thereby to form a single crystal semiconductor layer having an upper major surface with a second depression therein at a second, different reference position; and patterning the single crystal semiconductor layer using the second depression in the upper major surface of the semiconductor layer as a second alignment mark and thereby to form a semiconductor device in alignment with the device region in the semiconductor substrate, the first reference position of said first alignment mark being offset from the second reference position of the second alignment mark by an amount corresponding to, and thereby cancelling out, the expansion of the single crystal semiconductor layer caused by the recrystallizing step.
Claim 3
Dependent Claim
42 words
A method as claimed in claim 1 in which said semiconductor substrate has a generally circular configuration with a diameter of about 4 inches, said offset being about 1 μm in a radial direction toward a central part of the semiconductor substrate.
Claim 4
Dependent Claim
27 words
A method as claimed in claim 2 in which said first alignment mark is formed to oppose diametrically on the upper major surface of the semiconductor substrate.
Claim 5
Dependent Claim
33 words
A method as claimed in claim 1 wherein said recrystallizing step further comprises maintaining the semiconductor substrate at a temperature which does not cause migration of the impurity element from the diffusion region.
Claim 6
Dependent Claim
16 words
A method as claimed in claim 4 in which said temperature is 1200° C. or less.
Claim 7
Dependent Claim
14 words
A method as claimed in claim 5 in which said temperature is 1000° C.
Claim 8
Dependent Claim
81 words
A method as claimed in claim 1 wherein said patterning further comprises aligning a mask, which carries thereon an alignment mark and a device pattern relatively spaced by a distance identical with said selected distance between the first alignment mark and the device region on the upper major surface of the substrate, with respect to the single crystal semiconductor layer and such that the alignment mark of the mask aligns with the second alignment mark on the single crystal semiconductor layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-14 | 1997-09-13 | 1998-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-14 | 2001-09-13 | 2002-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-14 | 2005-09-13 | 2006-03-15 | $7700.00 | Window Closed / Lapsed |