Fabrication process for wafer alignment marks by using peripheral etching to form grooves

Claim 1

A wafer fabrication process comprising steps of: sequentially forming, on a first-conductive-type semiconductor substrate of a wafer, an oxide layer, an MoSi 2 layer, and a photoresist layer; opening windows in said photoresist layer for dopant diffusion and alignment mark formation, and removing the MoSi 2 layer from peripheral areas of said windows by peripheral etching; etching said oxide layer and said substrate to form grooves in areas from which said MoSi 2 layer has been removed; removing said photoresist and said MoSi 2 layer, forming an Si 3 N 4 layer on said wafer, then removing said Si 3 N 4 layer by anisotropic etching, leaving tapers of Si 3 N 4 in said grooves; diffusing a dopant through said windows and forming a drive-in oxide layer in areas not occupied by said tapers; removing said oxide layer, said drive-in oxide layer, and said tapers, and forming a second-conductive-type epitaxial semiconductor layer on said substrate; and aligning said wafer with a mask according to light scattered from said epitaxial semiconductor layer.