Semiconductor memory device having a data detection circuit with two reference potentials

Claim 2

A semiconductor memory device comprising: a memory cell for storing binary data, said cell being connected to a signal line to which a first load circuit is connected; a first reference cell storing a first logic level of binary data, said first reference cell being connected to a first reference line, a second load circuit having an identical current supply ability as that of said first load circuit and a first capacitor, for compensating parasitic capacitance of the signal line, both said second load circuit and said first capacitor being connected to said first reference line, wherein, since the second load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, a fluctuation in a power supply voltage has the same effect for both said memory cell and the first reference cell, thereby preventing an erroneous operation of the semiconductor memory device; a second reference cell storing a second logic level of binary data, said second reference cell being connected to a second reference line, a third load circuit having an identical current supply ability as that of said first load circuit and a second capacitor, for compensating parasitic capacitance of the signal line, both said third load circuit and said second capacitor being connected to said second reference line, wherein, since the third load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, the fluctuation in the power supply voltage has the same effect for both said memory cell and the second reference cell, thereby preventing an erroneous operation of the semiconductor memory device; and a data detection circuit for detecting the stored data of said memory cell, said data detection circuit having a first input, a second input, a third input and an output, said first input being connected to said signal line, said second input being connected to said first reference line, said third input being connected to said second reference line, said data detection circuit comparing a potential of said signal line with potentials of said first and second reference lines, a logic level of the output being determined by comparing the potential of said signal line with the potentials of said first and second reference lines.

Claim 3

A semiconductor memory device according to claim 1, wherein each of said first, second and third load circuits has a load resistance of the same value.

Claim 4

A semiconductor memory device according to claim 2, wherein each of said first, second and third load circuits has the same circuit configuration.

Claim 5

A semiconductor memory device according to claim 2, wherein said memory cell, said first reference cell and said second reference cell belonging to a corresponding row are connected to a common row line.

Claim 6

A semiconductor memory device according to claim 2, wherein said data detection circuit generates one of two logic levels of binary data from the output when the potential of said signal line is equal to the potential of said first reference line, said data detection circuit generates another of said two logic levels of binary data from the output when the potential of said signal line is equal to the potential of said second reference line.

Claim 7

A semiconductor memory device according to claim 5, wherein said data detection circuit is comprised of a differential sense amplifier.

Claim 8

A semiconductor memory device according to claim 6, wherein said differential sense amplifier includes a first input transistor connected to the first input, a second input transistor connected to the second input and a third input transistor connected to the third input, the potential of said signal line being applied to said first input transistor, the potential of said first reference line being applied to said second input transistor, the potential of said second reference line being applied to said third input transistor, said differential sense amplifier detecting said binary data stored in said memory cell by determining the difference between current flowing through said first input transistor and the sum of currents flowing through said second and third input transistors caused by the potentials of said signal line, said first reference line and said second reference line.

Claim 9

A semiconductor memory device according to claim 7 wherein said differential sense amplifier further comprises: first and second N channel transistors, gates thereof being commonly connected, and sources thereof being grounded, said first input transistor being a P channel transistor, the potential of the signal line being applied to the gate thereof, a power supply voltage being applied to the source thereof and the drain thereof being connected to the drain of said first N channel transistor, said second and third input transistors being P channel transistors, the potentials of said first and second reference lines being respectively applied to the gate thereof, the power supply voltage being applied to the sources thereof and the drains thereof being commonly connected to the drain and gate of said second N channel transistor, and detected data being taken out from the connection node between the drain of said first N channel transistor and the drains of said first input transistor.

Claim 10

A semiconductor memory device according to claim 7, wherein said differential sense amplifier further comprises: said first input transistor being an N channel transistor, the potential of said signal line being applied to the gate thereof, the power supply voltage being applied to the drain thereof, the source thereof being connected to a first pull down transistor, and said second and third input transistors being N channel transistors, the potentials of said first and second reference lines being respectively applied to the gates thereof, the power supply voltage being applied to the drains thereof, sources thereof being commonly connected to a second pull down transistor.

Claim 11

A semiconductor memory device according to claim 2, wherein leak means are provided for said second reference line, said leak means prevents said second reference line from electrically floating.

Claim 12

A semiconductor memory device comprising: a memory cell for storing binary data, said memory cell having a floating gate, said memory cell being connected to a signal line to which a first load circuit is connected, a logic state of the binary data stored in said memory cell being determined by whether or not electrons have been injected into said floating gate; a first reference cell storing a first logic level of binary data, said first reference cell being connected to a first reference line, a second load circuit having an identical current supply ability as that of said first load circuit and a first capacitor, for compensating parasitic capacitance of the signal line, both said second load circuit and said first capacitor being connected to said first reference line, said first logic level corresponding to said stored data of said memory cell when electrons are not injected in said floating gate, wherein, since the second load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, a fluctuation in a power supply voltage has the same effect for both said memory cell and the first reference cell, thereby preventing an erroneous operation of the semiconductor memory device; a second reference cell storing a second logic level of binary data, said second reference cell being connected to a second reference line, a third load circuit having an identical current supply ability to said first load circuit and a second capacitor, for compensating parasitic capacitance present on the signal line, both said third load circuit and said second capacitor being connected to said second reference cell, said second logic level corresponding to said stored data of said memory cell when electrons are injected in said floating gate, wherein, since the third load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, the fluctuation in the power supply voltage has the same effect for both said memory cell and the second reference cell, thereby preventing an erroneous operation of the semiconductor memory device; and a data detection circuit for detecting the stored data of said memory cell, said data detection circuit having a first input, a second input, a third input and an output, said first input being connected to said signal line, said second input being connected to said first reference line, said third input being connected to said second reference line, said data detection circuit comparing a potential of said signal line with potentials of said first and second reference lines, a logic level of the output being determined by comparing the potential of said signal line with the potentials of said first and second reference lines.

Claim 13

A semiconductor memory device comprising: a memory cell for storing binary data, said memory cell having a floating gate, said memory cell being connected to a signal line to which a first load circuit is connected, a logic state of the binary data stored in said memory cell being determined by whether or not electrons have been injected into said floating gate; a first reference cell storing a first logic level of binary data, said first reference cell being connected to a first reference line, a second load circuit having an identical current supply ability as that of said first load circuit and a first capacitor, for compensating parasitic capacitance of the signal line, both said second load circuit and said first capacitor being connected to said first reference line, said first logic level corresponding to said stored data of said memory cell when electrons are not injected in said floating gate, wherein, since the second load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, a fluctuation in a power supply voltage has the same effect for both said memory cell and the first reference cell, thereby preventing an erroneous operation of the semiconductor memory device; a second reference cell storing a second logic level of binary data, said second reference cell being connected to a second reference line, a third load circuit having an identical current supply ability to said first load circuit and a second capacitor, for compensating parasitic capacitance present on the signal line, both said third load circuit and said second capacitor being connected to said second reference cell, said second logic level corresponding to said stored data of said memory cell when electrons are injected in said floating gate, wherein, since the third load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, the fluctuation in the power supply voltage has the same effect for both said memory cell and the second reference cell, thereby preventing an erroneous operation of the semiconductor memory device; and a data detection circuit for detecting the stored data of said memory cell, said data detection circuit having a first input, a second input, a third input and an output, said first input being connected to said signal line, said second input being connected to said first reference line, said third input being connected to said second reference line, said data detection circuit comparing a potential of said signal line with potentials of said first and second reference lines, a logic level of the output being determined by comparing the potential of said signal line with the potentials of said first and second reference lines.

Claim 14

A semiconductor memory device according to claim 11, wherein each of said first, second and third load circuits has a load resistance of the same value.

Claim 15

A semiconductor memory device according to claim 12, wherein each of said first, second and third load circuits has the same circuit configuration.

Claim 16

A semiconductor memory device comprising: a memory array having a plurality of memory cells arranged in a matrix form with column lines and row lines, each of said memory cells storing binary data; a column decoder to select one of said column lines to which a first load circuit is connected; a row decoder to select one of said row lines; a first reference column line connecting a plurality of first reference cells, each of said first reference cells storing a first logic level of binary data, said first reference column line to which a second load circuit having an identical current supply ability as that of said first load circuit, and a first capacitor for compensating parasitic capacitance of the column line are connected, wherein, since the second load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, a fluctuation in a power supply voltage has the same effect for both said memory cell and the first reference cell, thereby preventing an erroneous operation of the semiconductor memory device; a second reference column line connecting a plurality of second reference cells, each of said second reference cells storing a second logic level of binary data, said second reference column line to which a third load circuit having an identical current supply ability as that of said first load circuit, and a second capacitor for compensating parasitic capacitance of the column line are connected, wherein, since the third load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, the fluctuation in the power supply voltage has the same effect for both said memory cell and the second reference cell, thereby preventing an erroneous operation of the semiconductor memory device; and a data detection circuit for detecting the stored data of said memory cells, said data detection circuit having a first input, a second input, a third input and an output, said first input being connected to selected one of said column lines, said second input being connected to said reference column line, said third input being connected to said second reference column line, said data detection circuit comparing a potential of said selected column line with potentials of said first and second reference column lines, a logic level of the output being determined by comparing the potential of said selected column line with the potentials of said first and second reference column lines.

Claim 17

A semiconductor memory device comprising: a memory array having a plurality of memory cells arranged in a matrix form with column lines and row lines, each of said memory cells storing binary data; a column decoder to select one of said column lines to which a first load circuit is connected; a row decoder to select one of said row lines; a first reference column line connecting a plurality of first reference cells, each of said first reference cells storing a first logic level of binary data, said first reference column line to which a second load circuit having an identical current supply ability as that of said first load circuit, and a first capacitor for compensating parasitic capacitance of the column line are connected, wherein, since the second load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, a fluctuation in a power supply voltage has the same effect for both said memory cell and the first reference cell, thereby preventing an erroneous operation of the semiconductor memory device; a second reference column line connecting a plurality of second reference cells, each of said second reference cells storing a second logic level of binary data, said second reference column line to which a third load circuit having an identical current supply ability as that of said first load circuit, and a second capacitor for compensating parasitic capacitance of the column line are connected, wherein, since the third load circuit and the first load circuit have the same circuit configuration and the same current supply abilities, the fluctuation in the power supply voltage has the same effect for both said memory cell and the second reference cell, thereby preventing an erroneous operation of the semiconductor memory device; and a data detection circuit for detecting the stored data of said memory cells, said data detection circuit having a first input, a second input, a third input and an output, said first input being connected to selected one of said column lines, said second input being connected to said reference column line, said third input being connected to said second reference column line, said data detection circuit comparing a potential of said selected column line with potentials of said first and second reference column lines, a logic level of the output being determined by comparing the potential of said selected column line with the potentials of said first and second reference column lines.

Claim 18

A semiconductor memory device according to claim 14, wherein said first and second reference column lines including first and second capacitance means respectively, and wherein a capacitance existing in said first reference column line to which said first capacitance means is connected is equal to a capacitance existing in one of said column lines, and a capacitance existing in said second reference column line to which said second capacitance means is connected is equal to a capacitance existing in one of said column lines.

Claim 19

A semiconductor memory device according to claim 14, wherein each of said first, second and third load circuits including first, second and third load transistors respectively, each of said first, second and third load transistors is the same size, each of said first, second and third load circuits has the same circuit configuration.

Claim 20

A semiconductor memory device according to claim 16, wherein said data detection circuit includes a first input transistor connected to the first input, a second input transistor connected to the second input and a third input transistor connected to the third input, the potential of said selected column line being applied to said first input transistor, the potential of said second reference column line being applied to said third input transistor, said data detection circuit detecting said binary data stored in said memory cell by the difference between a current flowing through said first input transistor and the sum of currents flowing through said second and third input transistors caused by the potentials of said selected column line, said first reference column line and said second reference column line.

Claim 21

A semiconductor memory device according to claim 17, wherein each of said memory cells having a floating gate, a logic state of the binary data stored said memory cell being determined by whether or not electrons are injected to said floating gate.