Memory device

Claim 2

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level and to a second threshold level below said first threshold level, said sensor means providing a read out output corresponding to the stored data of said selected memory cell such that when the data line potential exceeds said first threshold level, said sensor means provides a read out output representing said first state, and when the data line potential drops below said second threshold level, said sensor means provides a read out output representing said second state.

Claim 3

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; (d) first comparator means for comparing the data line potential with a first threshold level and generating a first comparison output when the data line potential exceeds the first threshold level; (e) second comparator means for comparing the data line potential with a second threshold level below said first threshold level and generating a second comparison output when the data line potential drops below the second threshold level; and (f) logic circuit means responsive to said first and second comparison outputs for providing a first stored data output according to the first comparison output and corresponding to said first state and providing a second stored data output according to the second comparison output and corresponding to said second state.

Claim 4

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; (d) first comparator means for comparing the data line potential with a first threshold level and generating a first comparison output when the data line potential exceeds the first threshold level; (e) second comparator means for comparing the data line potential with a second threshold level below said first threshold level and generating a second comparison output when the data line potential drops below the second threshold level; and (f) logic circuit means responsive to said first and second comparison outputs for providing a first stored data output according to the first comparison output and corresponding to said first state and providing a second stored data output according to the second comparison output and corresponding to said second state.

Claim 5

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a first data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said first data line, the potential of said first data line reflecting the state of the stored data of said selected memory cell; (d) differential amplifier means having a first input which receives the first data line potential and a second input which receives a second data line potential having an antiphase relationship to said data line potential for providing a read out output according to the potential difference between said first data line potential and second data line potential; (e) first sensitivity changer means coupled to the second input of said differential amplifier means and responsive to a first level corresponding to said data line potential for increasing the sensitivity of said second input; and (f) second sensitivity changer means coupled to the first input of said differential amplifier means and responsive to a second level corresponding to said second data line potential for increasing the sensitivity of said first input in which, when said first sensitivity changer means increases the second input sensitivity, said differential amplifier means provides a first stored data output corresponding to one logical state of said read out output, and when said second sensitivity changer means increases the first input sensitivity, said differential amplifier means provides a second stored data output corresponding to the other logical state of said read out output.

Claim 6

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a first data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said first data line, the potential of said first data line reflecting the state of the stored data of said selected memory cell; (d) differential amplifier means having a first input which receives the first data line potential and a second input which receives a second data line potential having an antiphase relationship to said data line potential for providing a read out output according to the potential difference between said first data line potential and second data line potential; (e) first sensitivity changer means coupled to the second input of said differential amplifier means and responsive to a first level corresponding to said data line potential for increasing the sensitivity of said second input; and (f) second sensitivity changer means coupled to the first input of said differential amplifier means and responsive to a second level corresponding to said second data line potential for increasing the sensitivity of said first input in which, when said first sensitivity changer means increases the second input sensitivity, said differential amplifier means provides a first stored data output corresponding to one logical state of said read out output, and when said second sensitivity changer means increases the first input sensitivity, said differential amplifier means provides a second stored data output corresponding to the other logical state of said read out output.

Claim 7

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; (d) first source means for providing a first threshold level; (e) second source means for providing a second threshold level; (f) comparator means responsive to the data line potential and one of said first and second threshold levels for providing a comparison result; (g) delay means coupled to said comparator means and responsive to said comparison result for providing selection information indicating the disappearance of a potential change of said data line potential; and (h) gate means coupled to said first source means, said second source means, said comparator means and said delay means and responsive to said selection information for gating said first threshold level and said second threshold level such that, when the data line potential corresponds to a first stored data, said gate means conducts said second threshold level to said comparator means, and when the data line potential corresponds to a second stored data, said gate means conducts said first threshold level to said comparator means.

Claim 8

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; (d) first source means for providing a first threshold level; (e) second source means for providing a second threshold level; (f) comparator means responsive to the data line potential and one of said first and second threshold levels for providing a comparison result; (g) delay means coupled to said comparator means and responsive to said comparison result for providing selection information indicating the disappearance of a potential change of said data line potential; and (h) gate means coupled to said first source means, said second source means, said comparator means and said delay means and responsive to said selection information for gating said first threshold level and said second threshold level such that, when the data line potential corresponds to a first stored data, said gate means conducts said second threshold level to said comparator means, and when the data line potential corresponds to a second stored data, said gate means conducts said first threshold level to said comparator means.

Claim 9

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; (d) first source means for providing a first threshold level; (e) second source means for providing a second threshold level; (f) comparator means responsive to the data line potential and one of said first and second threshold levels for providing a comparison result; (g) delay means reponsive to said data line potential for providing selection information indicating the disappearance of a potential change of said data line potential; and (h) gate means coupled to said first source means, said second source means, said comparator means and said delay means and responsive to said selection information for gating said first threshold level and second threshold level such that, when the data line potential corresponds to a first stored data, said gate means conducts said second threshold level to said comparator means, and when the data line potential corresponds to a second stored data, said gate means conducts said first threshold level to said comparator means.

Claim 10

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; (d) first source means for providing a first threshold level; (e) second source means for providing a second threshold level; (f) comparator means responsive to the data line potential and one of said first and second threshold levels for providing a comparison result; (g) delay means reponsive to said data line potential for providing selection information indicating the disappearance of a potential change of said data line potential; and (h) gate means coupled to said first source means, said second source means, said comparator means and said delay means and responsive to said selection information for gating said first threshold level and second threshold level such that, when the data line potential corresponds to a first stored data, said gate means conducts said second threshold level to said comparator means, and when the data line potential corresponds to a second stored data, said gate means conducts said first threshold level to said comparator means.

Claim 11

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line stored in said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; (d) a first transistor whose gate receives the data line potential; (e) a second transistor whose gate and source are respectively connected to the drain and source of said first transistor, and whose drain provides a read out output; (f) first impedance means connected between the source of said first transistor and a first power supply potential; (g) second impedance means connected between the drain of said first transistor and a second power supply potential; and (h) third impedance means connected between the drain of said second transistor and said second power supply potential, in which a source potential of said first transistor represents two potentials, one of which depends on the resistance ratio of said first and second impedance means and corresponds to a first threshold level, and the other of which depends on the resistance ratio of said first and third impedance means and corresponds to a second threshold level.

Claim 12

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line stored in said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; (d) a first transistor whose gate receives the data line potential; (e) a second transistor whose gate and source are respectively connected to the drain and source of said first transistor, and whose drain provides a read out output; (f) first impedance means connected between the source of said first transistor and a first power supply potential; (g) second impedance means connected between the drain of said first transistor and a second power supply potential; and (h) third impedance means connected between the drain of said second transistor and said second power supply potential, in which a source potential of said first transistor represents two potentials, one of which depends on the resistance ratio of said first and second impedance means and corresponds to a first threshold level, and the other of which depends on the resistance ratio of said first and third impedance means and corresponds to a second threshold level.

Claim 13

A memory device of claim 1, wherein said sensor means includes a differential amplifier having a first input which receives the data line potential and a second input which receives a second data line potential having an antiphase relationship to said first data line potential, said differential amplifier providing said read out output according to the potential difference between said first and second data line potentials.

Claim 14

A memory device of claim 1, wherein said sensor means includes a comparator responsive to said data line potential and one of said first and second threshold levels for providing a comparison result corresponding to said read out output.

Claim 15

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, for sensing the stored data of said selected memory cell from said data line potential, comparing said sensed stored data to a sense level and providing a read out output corresponding the sensed stored data, said sensor means including means responsive to the data stored in said selected memory cell for changing said sense level.

Claim 16

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, for sensing the stored data of said selected memory cell from said data line potential, comparing said sensed stored data to a sense level and providing a read out output corresponding the sensed stored data, said sensor means including means responsive to the data stored in said selected memory cell for changing said sense level.

Claim 17

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level, and to a second threshold level below said first threshold level, said sensor means including (i) a first comparator for comparing the data line potential with said first threshold level and generating a first comparison output when the data line potential exceeds said first threshold level, (ii) a second comparator for comparing of data line potential with said second threshold level and generating a second comparison output when the data line potential drops below said second threshold level, and (iii) a logic circuit responsive to said first and second comparison outputs for providing a first read out output according to said first comparison output and for providing a second read out output according to said second comparison output.

Claim 18

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level, and to a second threshold level below said first threshold level, said sensor means including (i) a first comparator for comparing the data line potential with said first threshold level and generating a first comparison output when the data line potential exceeds said first threshold level, (ii) a second comparator for comparing of data line potential with said second threshold level and generating a second comparison output when the data line potential drops below said second threshold level, and (iii) a logic circuit responsive to said first and second comparison outputs for providing a first read out output according to said first comparison output and for providing a second read out output according to said second comparison output.

Claim 19

A memory device of claim 10, wherein said first comparator generates said first comparison output at the time when the data line potential falls below the first threshold level; and said second comparator generates said second comparison output at the time when the data line potential exceeds the second threshold level.

Claim 20

A memory cell comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level and to a second threshold level below said first threshold level, said sensor means providing a read out output corresponding to the stored data of said selected memory cell such that when the data line potential exceeds said first threshold level, said sensor means provides a read out output representing said first state, and when the data line potential drops below said second threshold level, said sensor means provides a read out output representing said second state, and said sensor means also including (i) a differential amplifier having a first input receiving said data line potential and a second input receiving a second data line potential which has an antiphase relationship to said data line potential, said differential amplifier providing said read out output, (ii) a first sensitivity changer coupled to said second input of said differential amplifier and responsive to a first level corresponding to said data line potential, said sensitivity changer increasing the sensitivity of said second input, and (iii) a second sensitivity changer coupled to said first input of said differential amplifier and responsive to a second level corresponding to a said second data line potential, said second sensitivity changer increasing the sensitivity of said first input such that when said first sensitivity changer increases the sensitivity of said second input, said differential amplifier provides a read out output representing said first state, and when said second sensitivity changer increases the sensitivity of said first input, said differential amplifier provides a read out output representing said second state.

Claim 21

A memory cell comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level and to a second threshold level below said first threshold level, said sensor means providing a read out output corresponding to the stored data of said selected memory cell such that when the data line potential exceeds said first threshold level, said sensor means provides a read out output representing said first state, and when the data line potential drops below said second threshold level, said sensor means provides a read out output representing said second state, and said sensor means also including (i) a differential amplifier having a first input receiving said data line potential and a second input receiving a second data line potential which has an antiphase relationship to said data line potential, said differential amplifier providing said read out output, (ii) a first sensitivity changer coupled to said second input of said differential amplifier and responsive to a first level corresponding to said data line potential, said sensitivity changer increasing the sensitivity of said second input, and (iii) a second sensitivity changer coupled to said first input of said differential amplifier and responsive to a second level corresponding to a said second data line potential, said second sensitivity changer increasing the sensitivity of said first input such that when said first sensitivity changer increases the sensitivity of said second input, said differential amplifier provides a read out output representing said first state, and when said second sensitivity changer increases the sensitivity of said first input, said differential amplifier provides a read out output representing said second state.

Claim 22

A memory device of claim 12, wherein said sensor means further includes a delay circuit responsive to said data line potential for providing said first threshold level corresponding to a potential change point of said data line potential and being delayed by a given time so that the level change point of said first threshold level appears at the time when the corresponding potential change point of said data line potential disappears.

Claim 23

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selecting memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level and to a second threshold level below said first threshold level, said sensor means providing a read out output corresponding to the stored data of said selected memory cell such that when the data line potential exceeds said first threshold level, said sensor means provides a read out output representing said first state, and when the data line potential drops below said second threshold level, said sensor means provides a read out output representing said second state, said sensor means including (i) a first threshold level source for providing said first threshold level, (ii) a second threshold level source for providing said second threshold level, and (iii) a comparator responsive to said data line potential and to one of said first and second threshold levels for providing a comparison result corresponding to said read out output.

Claim 24

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selecting memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level and to a second threshold level below said first threshold level, said sensor means providing a read out output corresponding to the stored data of said selected memory cell such that when the data line potential exceeds said first threshold level, said sensor means provides a read out output representing said first state, and when the data line potential drops below said second threshold level, said sensor means provides a read out output representing said second state, said sensor means including (i) a first threshold level source for providing said first threshold level, (ii) a second threshold level source for providing said second threshold level, and (iii) a comparator responsive to said data line potential and to one of said first and second threshold levels for providing a comparison result corresponding to said read out output.

Claim 25

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level, and to a second threshold level below said first threshold level, said sensor means providing a read out output corresponding to the stored data of said selected memory cell such that when the data line potential exceeds said first threshold level, said sensor means provides a read out output representing said first state, and when the data line potential drops below said second threshold level, said sensor means provides a read out output representing said second state, said sensor means including (i) a comparator responsive to said data line potential and to one of said first and second threshold levels for providing a comparison result corresponding to said read out output, (ii) a delay circuit responsive to said data line potential for providing selection information indicating the disappearance of a change in said data line potential, and (iii) a gate circuit coupled to said comparator and to said delay circuit and responsive to said selection information for gating said first threshold level and said second threshold level such that when the data line potential corresponds to said second stored data, said gate circuit conducts said first threshold level to said comparator, and when the data line potential corresponds to said first stored data, said gate circuit conductor conducts said second threshold level to said comparator.

Claim 26

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level, and to a second threshold level below said first threshold level, said sensor means providing a read out output corresponding to the stored data of said selected memory cell such that when the data line potential exceeds said first threshold level, said sensor means provides a read out output representing said first state, and when the data line potential drops below said second threshold level, said sensor means provides a read out output representing said second state, said sensor means including (i) a comparator responsive to said data line potential and to one of said first and second threshold levels for providing a comparison result corresponding to said read out output, (ii) a delay circuit responsive to said data line potential for providing selection information indicating the disappearance of a change in said data line potential, and (iii) a gate circuit coupled to said comparator and to said delay circuit and responsive to said selection information for gating said first threshold level and said second threshold level such that when the data line potential corresponds to said second stored data, said gate circuit conducts said first threshold level to said comparator, and when the data line potential corresponds to said first stored data, said gate circuit conductor conducts said second threshold level to said comparator.

Claim 27

A memory device of claim 14, wherein said sensor means further includes a delay circuit coupled to said comparator and responsive to said comparison result for providing selection information indicating that a potential change point of said data line potential disappears; and a gate circuit coupled to said first threshold level source, said second threshold level source, said comparator and said delay circuit and responsive to said selection information for gating said first threshold level and second threshold level such that, when the data line potential corresponds to said second stored data, said gate circuit conducts said first threshold level to said comparator, and when the data line potential corresponds to said first stored data, said gate circuit conducts said second threshold level to said comparator.

Claim 28

A memory device of claim 16 or 15 wherein said sensor means further includes a timing circuit coupled to said comparator and delay circuit and responsive to said comparison result and said selection information, for providing a timing signal indicating a level change of said comparison result; and a latch circuit coupled to said timing circuit and comparator for latching the level of said comparison result according to said timing signal and providing the latched level as the read out output.

Claim 29

A memory device of claim 17, wherein said first threshold level corresponds to the maximum level of said data line potential, and said second threshold level corresponds to the maximum level of said data line potential.

Claim 30

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level, and to a second threshold level below said first threshold level, said sensor means providing a read out output corresponding to the stored data of said selected memory cell such that when the data line potential exceeds said first threshold level, said sensor means provides a read out output representing said first state, and when the data line potential drops below said second threshold level, said sensor means provides a read out output representing said second state, said sensor means including (i) a first transistor whose gate receives said data line potential, (ii) a second transistor whose gate and source are respectively connected to the drain and source of said first transistor, and whose drain provides said read out output, (iii) first impedance means connected between the source of said first transistor and a first power supply potential, (iv) second impedance means connected between the drain of said first transistor and a second power supply potential, and (v) third impedance means connected between the drain of said second transistor and said second power supply potential, such that a source potential of said first transistor represents two potentials, one of which depends on the resistance ratio of said first and second impedance means and corresponds to said first threshold level, and the other of which depends on the resistance ratio of said first and third impedance means and corresponds to said second threshold level.

Claim 31

A memory device comprising: (a) memory cells containing stored data in a first or second state; (b) a data line coupled to said memory cells for transferring data stored in said memory cells; (c) decoder means coupled to said memory cells for selecting one of said memory cells to be coupled to said data line, the potential of said data line reflecting the state of the stored data of said selected memory cell; and (d) sensor means coupled to said data line and responsive to the data line potential, to a first threshold level, and to a second threshold level below said first threshold level, said sensor means providing a read out output corresponding to the stored data of said selected memory cell such that when the data line potential exceeds said first threshold level, said sensor means provides a read out output representing said first state, and when the data line potential drops below said second threshold level, said sensor means provides a read out output representing said second state, said sensor means including (i) a first transistor whose gate receives said data line potential, (ii) a second transistor whose gate and source are respectively connected to the drain and source of said first transistor, and whose drain provides said read out output, (iii) first impedance means connected between the source of said first transistor and a first power supply potential, (iv) second impedance means connected between the drain of said first transistor and a second power supply potential, and (v) third impedance means connected between the drain of said second transistor and said second power supply potential, such that a source potential of said first transistor represents two potentials, one of which depends on the resistance ratio of said first and second impedance means and corresponds to said first threshold level, and the other of which depends on the resistance ratio of said first and third impedance means and corresponds to said second threshold level.

Claim 32

A memory device of any one of claims 2, 4-6, 13, 16, 11, wherein said first threshold level corresponds to the maximum level of said data line potential, and said second threshold level corresponds to the minimum level of said data line potential.