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US5289473A
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Method for determining byte error rate
Assignee: Nokia Bell Labs
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Filing: 1993-01-28
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Granted: 1994-02-22
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Expires: 2013-01-28
Abstract
Abstract A method is disclosed for determining the byte error rate (ByER) of a received digital signal. In particular, a local byte clock signal is generated and a complement of the received signal (or clock signal) is compared to the clock signal (or received signal). When both are the same logic value, as determined by a series of logic gates, an error is deemed to have occurred. The total number of errors N over a predetermined period of time T are then counted. The byte error rate is then determined from the relation ##EQU1##
Inventors
- 👤 Khanh C. Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:50
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/24
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
147 words
A method for determining the byte error rate in a received digital signal S, the method comprising the steps of: a) providing a byte clock signal C at a predetermined frequency; b) inverting either one of the received digital signal S and byte clock signal C (S or C) to form a complement signal; c) comparing the complement signal (S or C) to the other signal (C or S) and providing an output error signal E of logic value "1" when both said complement signal and said other signal comprise the same predetermined logic value; and d) counting each occurrence of the logic value "1" for error signal E and for providing as an output, after a predetermined period of time T, the total number N of said occurrences; and e) determining the byte error rate (ByER) of said received digital signal S from the relation ##EQU4##
Claim 2
Independent Claim
147 words
A method for determining the byte error rate in a received digital signal S, the method comprising the steps of: a) providing a byte clock signal C at a predetermined frequency; b) inverting either one of the received digital signal S and byte clock signal C (S or C) to form a complement signal; c) comparing the complement signal (S or C) to the other signal (C or S) and providing an output error signal E of logic value "1" when both said complement signal and said other signal comprise the same predetermined logic value; and d) counting each occurrence of the logic value "1" for error signal E and for providing as an output, after a predetermined period of time T, the total number N of said occurrences; and e) determining the byte error rate (ByER) of said received digital signal S from the relation ##EQU4##
Claim 3
Dependent Claim
67 words
The method as defined in claim 1 wherein in performing step b), the complement of the received digital signal, denoted S is formed; in performing step c), the complement received signal S is compared to the byte clock signal C, wherein the error signal E comprises a value of logic "1" when both said complement received signal S and byte clock signal C are logic "1" values.
Claim 4
Dependent Claim
66 words
The method as defined in claim 1 wherein in performing step b), the complement of the byte clock signal, denoted C is formed; in performing step c), the received signal S is compared to the complement byte clock signal C, wherein the error signal E comprises a value of logic "1" when both said received signal S and complement clock signal C are logic "0" values.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |