Badbit counter for memory testing

Claim 1

Apparatus for real-time recognizing and counting of digital device badbits in which a digital device under test (DUT) has at least one output, the apparatus comprising: a reference device, having an operating format corresponding to that of the DUT; a tester, providing clocking to exercise the DUT; the DUT and the reference device responsive in parallel to the tester; a comparing device, having a first input responsive to the DUT output, having a second input responsive to the reference device output, and having an output signal whose first state indicates that the first and second inputs are equivalent, and whose second state indicates that the first and second inputs are not equivalent, said inequivalencies being called badbits; a counter, having an input responsive to the comparing device output, counting badbits recognized by the comparing device; a flagbit latch, responsive to an initial digital transition of the comparing device output, indicating the occurrence of at least one badbit; the tester being responsive to one or more outputs of the apparatus; a conversion device having at least one input of a first sense and at least one output of a second sense, the inputs responsive to the counter outputs, for converting the count from the first sense to the second sense, the tester being responsive in said second sense to the conversion device output.