US3887869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for high speed digital circuit testing
Assignee: TAU TRON Inc
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Filing: 1972-07-25
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Granted: 1975-06-03
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Expires: 1992-07-25
Abstract
Abstract A complex digital circuit system such as a medium or a large scale integrated circuit is tested dynamically and functionally. The circuit is energized repeatedly with different sets of input signals and output signals are compared with standards. The sets of input signals successively energize the circuit at a rate of the same order of magnitude as the rate of intended operation of the circuit and the sets define a pseudo-random sequence in which each set is different. The sequence of test signals is conveniently produced by a multistage shift register having feedback loops structured and controlled to produce the particular sequence, the beginning and end of any given sequence being predetermined by a computer or operator.
Inventors
- 👤 John B Connolly
- 👤 Yohan Cho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:31
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318385; G01R31/31813
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
258 words
A system for testing a complex electronic circuit where the same set of input signals are simultaneously applied to a test circuit and a standard circuit and output signals from the test and standard circuits are simultaneously compared to detect a fault in the test circuit comprising, a random number generator for generating random parallel binary numbers of up to N bits each at a rate in the dynamic operating range of the test circuit, each random number being represented as a set of N generator output signals, means applying said N output signals to inputs of both the test and standard circuits which produces in response thereto, test and standard sets of M output signals, a set of M coincidence comparing circuits, each responsive to corresponding output signals from the test and standard circuits, said M comparing circuits producing a set of M fault signals, an N stage register for storing a random number, an M stage register for storing M fault output signals, means responsive to the M fault output signals for feeding the particular random number applied to the test and standard circuits, which results in at least one fault output signal from the comparing circuits, to the N stage register, and means responsive to the M fault output signals for feeding the fault output signals to the M stage register at the same time the said particular random number is fed to the N stage register, whereby said registers store information indicative of inputs and outputs of the test circuit when a fault occurs.
Claim 2
Independent Claim
258 words
A system for testing a complex electronic circuit where the same set of input signals are simultaneously applied to a test circuit and a standard circuit and output signals from the test and standard circuits are simultaneously compared to detect a fault in the test circuit comprising, a random number generator for generating random parallel binary numbers of up to N bits each at a rate in the dynamic operating range of the test circuit, each random number being represented as a set of N generator output signals, means applying said N output signals to inputs of both the test and standard circuits which produces in response thereto, test and standard sets of M output signals, a set of M coincidence comparing circuits, each responsive to corresponding output signals from the test and standard circuits, said M comparing circuits producing a set of M fault signals, an N stage register for storing a random number, an M stage register for storing M fault output signals, means responsive to the M fault output signals for feeding the particular random number applied to the test and standard circuits, which results in at least one fault output signal from the comparing circuits, to the N stage register, and means responsive to the M fault output signals for feeding the fault output signals to the M stage register at the same time the said particular random number is fed to the N stage register, whereby said registers store information indicative of inputs and outputs of the test circuit when a fault occurs.
Claim 3
Independent Claim
258 words
A system for testing a complex electronic circuit where the same set of input signals are simultaneously applied to a test circuit and a standard circuit and output signals from the test and standard circuits are simultaneously compared to detect a fault in the test circuit comprising, a random number generator for generating random parallel binary numbers of up to N bits each at a rate in the dynamic operating range of the test circuit, each random number being represented as a set of N generator output signals, means applying said N output signals to inputs of both the test and standard circuits which produces in response thereto, test and standard sets of M output signals, a set of M coincidence comparing circuits, each responsive to corresponding output signals from the test and standard circuits, said M comparing circuits producing a set of M fault signals, an N stage register for storing a random number, an M stage register for storing M fault output signals, means responsive to the M fault output signals for feeding the particular random number applied to the test and standard circuits, which results in at least one fault output signal from the comparing circuits, to the N stage register, and means responsive to the M fault output signals for feeding the fault output signals to the M stage register at the same time the said particular random number is fed to the N stage register, whereby said registers store information indicative of inputs and outputs of the test circuit when a fault occurs.
Claim 4
Independent Claim
258 words
A system for testing a complex electronic circuit where the same set of input signals are simultaneously applied to a test circuit and a standard circuit and output signals from the test and standard circuits are simultaneously compared to detect a fault in the test circuit comprising, a random number generator for generating random parallel binary numbers of up to N bits each at a rate in the dynamic operating range of the test circuit, each random number being represented as a set of N generator output signals, means applying said N output signals to inputs of both the test and standard circuits which produces in response thereto, test and standard sets of M output signals, a set of M coincidence comparing circuits, each responsive to corresponding output signals from the test and standard circuits, said M comparing circuits producing a set of M fault signals, an N stage register for storing a random number, an M stage register for storing M fault output signals, means responsive to the M fault output signals for feeding the particular random number applied to the test and standard circuits, which results in at least one fault output signal from the comparing circuits, to the N stage register, and means responsive to the M fault output signals for feeding the fault output signals to the M stage register at the same time the said particular random number is fed to the N stage register, whereby said registers store information indicative of inputs and outputs of the test circuit when a fault occurs.
Claim 5
Dependent Claim
36 words
A system as in claim 1 wherein, the last mentioned means includes, an OR circuit responsive to the M fault signals, and the OR circuit controls the input to both the N and M stage registers.
Claim 6
Dependent Claim
60 words
A system as in claim 1 further including, means for generating a predetermined random sequence start number and stop number, and means in circuit with the generator, responsive to said start and stop numbers for comparing the same with the generated number, and means responsive thereto for starting and stopping the applying of generator output signals to the test circuit.
References Cited (Backward Citations)
US3286175A
Cited
US3614608A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-02 | 1978-12-02 | 1979-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-02 | 1982-12-02 | 1983-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-02 | 1986-12-02 | 1987-06-03 | $7700.00 | Window Closed / Lapsed |