Data error detector for determining the error rate prior to equalization

Claim 2

In a data transmission system having a data transmitter, a data receiver and a transmission medium connected therebetween, apparatus for detecting errors in an unequalized data signal received at the receiver comprising: a transversal filter in said data receiver having an input for accepting the unequalized data signal, an output, and means for converting said unequalized input data signal into an equalized binary data signal which is applied to said output; first circuit means having an output and an input which is operatively connected to said transversal filter, said first circuit means providing an equalized data signal at said output; second circuit means having an output and an input which is operatively connected to said transversal filter, said second circuit means providing an unequalized data signal at said output; a comparator having an output and a plurality of inputs, a first said input being operatively connected to the output of the first circuit means and a second said input being operatively connected to the output of said second circuit means and means for generating an error signal at said output when a comparison of the inputs from said first and second circuit means indicates that an error has occurred; and error indicating means connected to the output of said comparator to provide, in response to said error signal, an indication of the transmission errors in the input data signal.

Claim 3

Error detEcting apparatus in a data receiver as claimed in claim 1, wherein said first circuit means is connected at the output of said transversal filter, and said second circuit means is connected to the input of said transversal filter, said second circuit means including time delay means for providing a time delay of substantially the same duration as that caused by the passage of the unequalized data signal through the transversal filter.

Claim 4

Error detecting apparatus as claimed in claim 2, wherein said second circuit means includes means for changing the unequalized data signal into a binary representation of said signal.

Claim 5

Error detecting apparatus as claimed in claim 1, wherein said transversal filter includes a tapped delay line with a plurality of taps including a main tap, said first circuit means being operatively connected to the output of said transversal filter and said second circuit means being operatively connected to said main tap.

Claim 6

Error detecting apparatus as claimed in claim 1, wherein said transversal filter comprises means for converting said unequalized data signal into an n-digit binary code having a most significant digit determinative of the binary representation of said unequalized data signal, and wherein said second circuit means is connected to said converting means.

Claim 7

Error detecting apparatus as claimed in claim 1, wherein said transversal filter comprises sampling means for changing said unequalized data signal into pulse amplitude modulation samples, quantizing means connected to said sampling means for changing said pulse amplitude modulation samples into n-digit binary signals having a most significant digit, binary arithmetic means connected to said quantizing means for providing an equalized n-digit output and a binary output representative of said unequalized data signal, decoding means for changing said unequalized n-digit output into an equalized binary data signal, and clock means to provide timing signals to the quantizing, arithmetic and decoding means; and wherein the input of said second circuit means is connected to said binary output representative of said unequalized data signal.

Claim 8

Error detecting apparatus as claimed in claim 4, wherein said comparator comprises an EXclusive-OR gate.

Claim 9

Error detecting apparatus as claimed in claim 5, wherein said first circuit means is connected to the output of said transversal filter.

Claim 10

Error detecting apparatus as claimed in claim 6 wherein said comparator further comprises: a timing means; a first logic means having an input operatively connected to the transversal filter to select from said filter a binary signal representative of said equalized data signal, said first logic means having first and second outputs which provide at said outputs complementary binary signals in response to the equalized data signal applied to the input the order of the complementary signals being upright when the input is 1 and in inverted order when the input is 0: a memory means having a first input operatively connected to said timing means and a second input operatively connected to the transversal filter to select from said filter a binary signal representative of said unequalized data signal, said first logic means having first and second outputs which provide at said outputs complementary binary signals at the timing rate in response to the unequalized data signal at the second input, the order of the complementary signals at said outputs being upright, i.e., first output is 0 and second output is 1 when the unequalized data signal input is 1, and inverted, i.e., 1 and 0, respectively, when the unequalized data signal is 0; a second logic means having a plurality of inputs, and an output, one each of said inputs being operatively connected to an output of said first logic and said memory means, said second logic means providing an output of one binary state when the complementary States of the first logic means and the memory means are alike, i.e., both are either upright or inverted, and providing an output of the other binary state when the complementary states of the logic means and memory means are unlike, i.e., one is upright and the other is inverted; delay means having an input connected to said timing means, an output, said delay means providing a time delay to the timing means output of the same magnitude as that experienced by the unequalized signal in passing through said memory means and said second logic means; a gating means having a first input connected to the output of said delay means, a second input connected to the output of said second logic means, and an output, said gating means providing an output of one binary state when the input from the second logic means is of one binary condition and an output of a second binary state when the input from the second logic means is in the other binary condition.