US5283479A — BiCMOS logic gate having plural linearly operated…

Claim 1

Independent Claim 112 words

An improved BiCMOS logic circuit which includes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a first reference potential, each of said bipolar transistors being coupled to a resistive load network, wherein the improvement comprises: a plurality of metal-oxide-semiconductor (MOS) transistors coupled in parallel between a first operating potential and the collector of each bipolar transistor, at least one of said MOS transistors providing a fixed resistance and at least one other of said MOS transistors being linearly-operated and having its gate coupled to a variable control voltage to provide a variable resistance thereof, the parallel combination of said MOS transistors improving the linearity of said circuit.

Claim 2

Dependent Claim 112 words

An improved BiCMOS logic circuit which includes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a first reference potential, each of said bipolar transistors being coupled to a resistive load network, wherein the improvement comprises: a plurality of metal-oxide-semiconductor (MOS) transistors coupled in parallel between a first operating potential and the collector of each bipolar transistor, at least one of said MOS transistors providing a fixed resistance and at least one other of said MOS transistors being linearly-operated and having its gate coupled to a variable control voltage to provide a variable resistance thereof, the parallel combination of said MOS transistors improving the linearity of said circuit.

Claim 3

Dependent Claim 14 words

The logic circuit of claim 1 wherein said MOS transistors comprise p-channel (PMOS) devices.

Claim 4

Dependent Claim 14 words

The logic circuit of claim 1 wherein said MOS transistors comprise n-channel (NMOS) devices.

Claim 5

Dependent Claim 35 words

The logic circuit of claim 2 wherein said at least one of said PMOS transistors has its gate coupled to a second operating potential, said second operating potential being lower than said first operating potential.

Claim 6

Dependent Claim 24 words

The logic circuit of claim 2 wherein said at least one of said PMOS transistors has its gate coupled to said first operating potential.

Claim 7

Dependent Claim 18 words

The circuit of claim 5 wherein said variable resistance is relatively high as compared to said fixed resistance.

Claim 8

Dependent Claim 18 words

The circuit of claim 4 wherein said fixed resistance is relatively high as compared to said variable resistance.

Claim 9

Dependent Claim 38 words

The circuit of either claim 6 or 7 further comprising an amplifier for generating said control voltage, said amplifier adjusting said control voltage to maintain a constant logic swing across said resistive load network over a temperature range.

Claim 10

Dependent Claim 11 words

The circuit of claim 8 wherein said logic swing is ECL-compatible.

Claim 11

Dependent Claim 30 words

The circuit of claim 8 wherein said first operating potential comprises the highest positive supply potential coupled to said circuit, and said second operating potential comprises the lowest supply potential.

Claim 12

Dependent Claim 136 words

An improved BiCMOS logic circuit which includes an emitter-coupled pair of bipolar transistors for differentially comparing an input control signal with a first reference potential, each of said bipolar transistors being loaded by a linearly-operated p-channel metal-oxide-semiconductor (PMOS) transistor coupled between its collector and a first operating potential, the gates of said field-effect transistors being coupled to a second reference potential which determines the load resistance of said circuit, said circuit further comprising a means for biasing said emitter-coupled pair, said biasing means comprising a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors coupled in parallel between the emitters of said emitter-coupled pair and said second operating potential, at least one of the gates of said NMOS transistors being coupled to a control signal which regulates the switching current provided by said biasing means to said emitter-coupled pair.

Claim 13

Dependent Claim 136 words

An improved BiCMOS logic circuit which includes an emitter-coupled pair of bipolar transistors for differentially comparing an input control signal with a first reference potential, each of said bipolar transistors being loaded by a linearly-operated p-channel metal-oxide-semiconductor (PMOS) transistor coupled between its collector and a first operating potential, the gates of said field-effect transistors being coupled to a second reference potential which determines the load resistance of said circuit, said circuit further comprising a means for biasing said emitter-coupled pair, said biasing means comprising a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors coupled in parallel between the emitters of said emitter-coupled pair and said second operating potential, at least one of the gates of said NMOS transistors being coupled to a control signal which regulates the switching current provided by said biasing means to said emitter-coupled pair.

Claim 14

Dependent Claim 31 words

The logic circuit of claim 11 further comprising an amplifier for generating said control signal, said amplifier adjusting said control signal to maintain a constant logic swing across said load resistance.

Claim 15

Dependent Claim 13 words

The logic circuit of claim 12 wherein said logic swing is ECL compatible.

Claim 16

Dependent Claim 35 words

The logic circuit of claim 13 wherein said first operating potential comprises the highest positive supply potential coupled to said circuit and said second operating potential comprises the lowest supply potential coupled to said circuit.

Claim 17

Dependent Claim 33 words

The logic circuit of claim 13 wherein at least one of said NMOS transistors has its gate coupled to said second operating potential thereby providing a fixed current component of said switching current.

Claim 18

Dependent Claim 137 words

An improved BiCMOS logic circuit which comprises: an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a first reference potential; a current source means for biasing said emitter-coupled pair; a means for resistively loading each of said bipolar transistors; said loading means comprising a plurality of N, where N is an integer, MOS transistors coupled in parallel, the Nth transistor in said set providing a relative resistance calculated as 2 N , said MOS transistors being coupled in parallel between a first operating potential and the collector of one said bipolar transistors; and a digital switching means for activating selected ones of said MOS transistors to provide a predetermined load resistance to one of said bipolar transistors, said switching means activating a selected MOS transistor by coupling a high voltage to its gate.

Claim 19

Dependent Claim 137 words

An improved BiCMOS logic circuit which comprises: an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a first reference potential; a current source means for biasing said emitter-coupled pair; a means for resistively loading each of said bipolar transistors; said loading means comprising a plurality of N, where N is an integer, MOS transistors coupled in parallel, the Nth transistor in said set providing a relative resistance calculated as 2 N , said MOS transistors being coupled in parallel between a first operating potential and the collector of one said bipolar transistors; and a digital switching means for activating selected ones of said MOS transistors to provide a predetermined load resistance to one of said bipolar transistors, said switching means activating a selected MOS transistor by coupling a high voltage to its gate.

Claim 20

Dependent Claim 13 words

The circuit of claim 16 wherein said MOS transistors comprise p-channel (PMOS) devices.

Claim 21

Dependent Claim 13 words

The circuit of claim 16 wherein said MOS transistors comprise n-channel (NMOS) devices.

Claim 22

Dependent Claim 17 words

The circuit of claim 17 wherein said high voltage is approximately equal to said first operating potential.

Claim 23

Dependent Claim 18 words

The logic circuit of claim 17 wherein each of said PMOS transistors has a different relative device size.

Claim 24

Dependent Claim 55 words

The logic circuit of claim 20 wherein said switching means comprises a parallel connection of N inverters, each of said inverters providing either said operating potential or a controlled voltage signal to the gates of corresponding ones of said set of PMOS transistors, wherein said control voltage signal is less than said first operating potential.

Claim 25

Dependent Claim 35 words

The logic circuit of claim 21 further comprising an amplifier for generating said controlled voltage signal, said amplifier adjusting said control voltage signal to maintain a constant logic swing across said plurality of PMOS transistors.

Claim 26

Dependent Claim 122 words

A BiCMOS logic circuit comprising; an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a first reference potential; a means for loading each of said bipolar transistors, said loading means comprising a pair of linearly-operated metal-oxide-semiconductor transistors, each of said MOS transistors being coupled between the collector of a corresponding bipolar transistor of said emitter-coupled pair and a first operating potential, the gates of said MOS transistors being coupled to a second reference potential; a first biasing means for biasing said emitter-coupled pair; and a circuit means providing a control signal to said first biasing means for controlling the current flow through said emitter-coupled pair, said current flow also determining the load resistance presented by said MOS transistors.

Claim 27

Dependent Claim 122 words

A BiCMOS logic circuit comprising; an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a first reference potential; a means for loading each of said bipolar transistors, said loading means comprising a pair of linearly-operated metal-oxide-semiconductor transistors, each of said MOS transistors being coupled between the collector of a corresponding bipolar transistor of said emitter-coupled pair and a first operating potential, the gates of said MOS transistors being coupled to a second reference potential; a first biasing means for biasing said emitter-coupled pair; and a circuit means providing a control signal to said first biasing means for controlling the current flow through said emitter-coupled pair, said current flow also determining the load resistance presented by said MOS transistors.

Claim 28

Dependent Claim 14 words

The logic circuit of claim 23 wherein said MOS transistors comprise p-channel (PMOS) devices.

Claim 29

Dependent Claim 14 words

The logic circuit of claim 23 wherein said MOS transistors comprise n-channel (NMOS) devices.

Claim 30

Dependent Claim 29 words

The logic circuit of either claim 24 or 25 wherein said circuit means is coupled to a third reference potential which determines the output swing of said logic circuit.

Claim 31

Dependent Claim 43 words

The logic circuit of claim 26 further comprising: an emitter follower transistor having its base coupled to the collector of one of said bipolar transistors to provide an ECL-compatible output logic swing; and a second biasing means for biasing said emitter follower transistor.

Claim 32

Dependent Claim 24 words

The logic circuit of claim 27 wherein said control signal maintains the ECL compatibility of said output swing over temperature, supply and process variations.

Claim 33

Dependent Claim 12 words

The logic circuit of claim 23 wherein said PMOS transistors are matched.

Claim 34

Dependent Claim 41 words

The logic circuit of claim 28 wherein said first biasing means comprises a first n-channel metal-oxide-semiconductor (NMOS) transistor coupled between said emitter-coupled pair and a second operating potential, said first NMOS transistor having its gate coupled to receive said control signal.

Claim 35

Dependent Claim 70 words

The logic circuit of claim 30 wherein said circuit means comprises a reference PMOS transistor having its gate coupled to said second reference potential, and an amplifier means for generating said control signal from a comparison of the drain potential of said reference PMOS transistor and said second reference potential, said amplifier means adjusting said control signal so that said drain potential is approximately equal to said second reference potential.

Claim 36

Dependent Claim 40 words

The logic circuit of claim 31 wherein said circuit means further comprises a second NMOS transistor coupled between said reference PMOS transistor and said second operating potential, said second NMOS transistor having its gate coupled to receive said control signal.

Claim 37

Dependent Claim 14 words

The logic circuit of claim 32 wherein said amplifier means comprises an operational amplifier.

Claim 38

Dependent Claim 26 words

The logic circuit of claim 33 wherein said reference PMOS transistor is matched to said PMOS transistors, and said first and second NMOS transistors are matched.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-01-31	1997-08-02	1998-02-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-01-31	2001-08-02	2002-02-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-01-31	2005-08-02	2006-02-01	$7700.00	Window Closed / Lapsed

BiCMOS logic gate having plural linearly operated load FETs

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