MESFET with indium gallium arsenide etch stop

Claim 2

A field effect transistor, comprising: a channel region overlying a semiconductor substrate and defined in a channel layer of a first semiconductor material; a gate overlying said channel region; an etch stop layer adjacent said gate and overlying said channel region, said etch stop layer comprising a second semiconductor material different than said first semiconductor material, wherein said etch stop layer is substantially undoped and abuts said gate and is separated from said channel region by a material with a bandgap wider than a bandgap of said etch stop layer and a bandgap of said channel region material; a source overlying said etch stop layer; and a drain overlying said etch stop layer.

Claim 3

A field effect transistor comprising: a substrate having an epitaxial layer of a first semiconductor material; an unetched channel region overlying said substrate and defined in said epitaxial layer; a gate overlying said channel region; a source overlying said channel region; a drain overlying said channel region; and an etch stop layer of a second semiconductor material different than said first semiconductor material overlying said channel region, said channel region on one side of said etch stop layer and said gate, source and drain on the other side, wherein said etch stop layer is undoped and abuts said gate and is separated from said channel region by a material with a bandgap wider than a bandgap of said etch stop layer and a bandgap of said channel region material.

Claim 4

A field effect transistor comprising: a substrate having an epitaxial layer of a first semiconductor material; an unetched channel region overlying said substrate and defined in said epitaxial layer; a gate overlying said channel region; a source overlying said channel region; a drain overlying said channel region; and an etch stop layer of a second semiconductor material different than said first semiconductor material overlying said channel region, said channel region on one side of said etch stop layer and said gate, source and drain on the other side, wherein said etch stop layer is undoped and abuts said gate and is separated from said channel region by a material with a bandgap wider than a bandgap of said etch stop layer and a bandgap of said channel region material.

Claim 5

The transistor of claim 1 wherein said channel layer comprises n-doped GaAs.

Claim 6

The transistor of claim 1 wherein said etch stop layer comprises In y Ga 1-y As.

Claim 7

The transistor of claim 4 wherein y is about 0.01.

Claim 8

The transistor of claim 1 wherein said source and said drain comprise GaAs.

Claim 9

The transistor of claim 1 wherein said gate comprises a Ti/Pt/Au Schottky gate.

Claim 10

A metal semiconductor field effect transistor comprising: a semi-insulating GaAs substrate; a GaAs channel layer overlying said substrate; an In y Ga 1-y As etch stop layer overlying said channel layer, wherein y is about 0.01; a GaAs source overlying said etch stop layer; a GaAs drain overlying said etch stop layer; and a gate overlying said channel layer.

Claim 11

A metal semiconductor field effect transistor comprising: a semi-insulating GaAs substrate; a GaAs channel layer overlying said substrate; an In y Ga 1-y As etch stop layer overlying said channel layer, wherein y is about 0.01; a GaAs source overlying said etch stop layer; a GaAs drain overlying said etch stop layer; and a gate overlying said channel layer.

Claim 12

The transistor of claim 8 wherein said wherein said GaAs channel layer comprises an n-doped GaAs layer.

Claim 13

The transistor of claim 8 wherein said channel layer is about 1000 Å thick.

Claim 14

The transistor of claim 8 wherein said source and drain comprise n + GaAs.

Claim 15

The transistor of claim 8 wherein said etch stop layer is between about 25 Å and 100 Å thick.

Claim 16

The transistor of claim 8 wherein said etch stop layer is substantially undoped.

Claim 17

The transistor of claim 8 wherein said gate comprises a Ti/Pt/Au Schottky gate.

Claim 18

The transistor of claim 8 further comprising a source ohmic contact overlying said source and a drain ohmic contact overlying said drain.

Claim 19

A field effect transistor, comprising: a channel region overlying a semiconductor substrate and defined in a channel layer of a semiconductor material other than In y Ga 1-y As, where y is about 0.01; a gate overlying said channel region; an In y Ga 1-y As etch stop layer adjacent said gate and overlying said channel region, wherein y is about 0.01; a source overlying said etch stop layer; and a drain overlying said etch stop layer.

Claim 20

A field effect transistor, comprising: a channel region overlying a semiconductor substrate and defined in a channel layer of a semiconductor material other than In y Ga 1-y As, where y is about 0.01; a gate overlying said channel region; an In y Ga 1-y As etch stop layer adjacent said gate and overlying said channel region, wherein y is about 0.01; a source overlying said etch stop layer; and a drain overlying said etch stop layer.

Claim 21

A metal semiconductor field effect transistor comprising: a semi-insulating GaAs substrate; a GaAs channel layer overlying said substrate; an In y Ga 1-y As etch stop layer overlying said channel layer, wherein said etch stop layer is substantially undoped and is separated from said channel region by a material with a bandgap wider than a bandgap of said etch stop layer and a bandgap of said channel region layer; a GaAs source overlying said etch stop layer; a GaAs drain overlying said etch stop layer; and a gate overlying said channel layer.

Claim 22

A metal semiconductor field effect transistor comprising: a semi-insulating GaAs substrate; a GaAs channel layer overlying said substrate; an In y Ga 1-y As etch stop layer overlying said channel layer, wherein said etch stop layer is substantially undoped and is separated from said channel region by a material with a bandgap wider than a bandgap of said etch stop layer and a bandgap of said channel region layer; a GaAs source overlying said etch stop layer; a GaAs drain overlying said etch stop layer; and a gate overlying said channel layer.