Abstract The disclosed device is a field-effect transistor which includes a support region that may typically comprise a substrate having a buffer layer thereon. A semiconductor channel layer of one conductivity type is disposed on the support region. A first highly-doped semiconductor layer of opposite conductivity type is disposed on the channel layer. A second highly-doped semiconductor layer of said one conductivity type is disposed on the first highly-doped semiconductor layer. Source and drain electrodes are disposed in spaced relation, and contact the channel layer. A gate electrode is disposed on the second highly-doped semiconductor layer in the region between the source and drain electrodes. In a preferred embodiment, the source and drain electrodes are disposed on the second highly-doped semiconductor layer and extend through the second and first highly-doped semiconductor layers to the channel layer. The first and second highly-doped layers are thin enough to be fully depleted by adjacent layers. This being the case, it is not necessary to etch these highly-doped layers in the regions between the gate and the source and drain electrodes, since they do not act as current-carrying paths.
Inventors
👤 Hadis Morkoc
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-30 05:53
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
100 words
A field-effect transistor device, comprising: a support region; a semiconductor channel layer of one conductivity type disposed on the support region; a first highly-doped semiconductor layer of opposite conductivity type disposed on said channel layer; a second highly-doped semiconductor layer of said one conductivity type disposed on said first highly-doped semiconductor layer; source and drain electrodes disposed in spaced relation on said second higly-doped semiconductor layer and extending through said second and first highly-doped semiconductor layers to said channel layer; and a gate electrode disposed on said second highly-doped semiconductor layer in the region between said source and drain electrodes.
Claim 2
Dependent Claim
100 words
A field-effect transistor device, comprising: a support region; a semiconductor channel layer of one conductivity type disposed on the support region; a first highly-doped semiconductor layer of opposite conductivity type disposed on said channel layer; a second highly-doped semiconductor layer of said one conductivity type disposed on said first highly-doped semiconductor layer; source and drain electrodes disposed in spaced relation on said second higly-doped semiconductor layer and extending through said second and first highly-doped semiconductor layers to said channel layer; and a gate electrode disposed on said second highly-doped semiconductor layer in the region between said source and drain electrodes.
Claim 3
Dependent Claim
24 words
The device as defined by claim 1, wherein said first and second highly-doped layers are thin enough to be fully depleted by adjacent layers.
Claim 4
Dependent Claim
21 words
The device as defined by claim 1, wherein said one conductivity type is n-type and said opposite conductivity type is p-type.
Claim 5
Dependent Claim
43 words
The device as defined by claim 1, wherein said channel layer and said second highly-doped layer are formed of gallium arsenide and said first highly-doped layer is formed of a semiconductor selected from the group consisting of gallium arsenide and aluminum gallium arsenide.
Claim 6
Dependent Claim
22 words
The device as defined by claim 4, wherein said highly doped semiconductor layers have at least 10 18 carriers per cubic centimeter.
Claim 7
Dependent Claim
21 words
The device as defined by claim 1, wherein said support region comprises a substrate having a high-resistivity semiconductor buffer layer thereon.
Claim 8
Dependent Claim
21 words
The device as defined by claim 1, wherein said gate electrode forms an ohmic contact with said second highly-doped semiconductor layer.