Patent US3304192A successfully refreshed from Google Patents.
Patent US5281843A successfully refreshed from Google Patents.
US5281843A
Expired / Lapsed
US
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Thin-film transistor, free from parasitic operation
Assignee: Toshiba Corp
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Filing: 1991-06-19
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Granted: 1994-01-25
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Expires: 2011-06-19
Abstract
Abstract First and second N-channel MOS transistors, each serving as a transfer gate, have their current paths connected, at their first ends, to bit lines, respectively, and their gates connected to a word line. Third and fourth N-channel MOS transistors, forming a flip-flop circuit, have their current paths connected, at their first ends, to the second ends of the current paths of the first and second transistors, respectively, and at their second ends, to a first power supply. The first ends of the current paths of the third and fourth transistors are connected to first ends of first and second thin-film transistors, respectively. The second ends of the current paths of the first and second thin-film transistors are connected to a second power supply. Each of the first and second thin-film transistors has first and second gates on both sides of its channel region. The first and second gates of the first thin-film transistor are connected to the gate of the fourth transistor, while the first and second gates of the second thin-film transistor are connected to the gate of the third transistor. Thus, the first and second thin-film transistors are supplied with a potential to render them nonconductive.
Inventors
- 👤 Kiyofumi Ochii
- 👤 Shigeyuki Hayakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H10B; H10B10/00; H10B10/12; H10B10/125; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
335 words
A semiconductor memory device, using a thin-film transistor as a load, comprising: first and second insulated gate transistors of a first conductivity type each having a current path and a gate, first ends of said current paths of said first and second insulated gate transistors being respectively connected to bit lines, and said gates of said first and second insulated gate transistors being connected to a word line; third and fourth insulated gate transistors of said first conductivity type, each having a current path and a gate, first ends of said current paths of said third and fourth insulated gate transistors being respectively connected to second ends of said current paths of said first and second insulated gate transistors, second ends of said current paths of said third and fourth insulated gate transistors being connected to a first power supply, said gate of said third insulated gate transistor being connected to said second end of said current path of said second insulated gate transistor, and said gate of said fourth insulated gate transistor being connected to said second end of said current path of said first insulated gate transistor; and first and second thin-film transistors of a second conductivity type each having a current path, and respectively having first and second channel regions, first ends of said current paths of said first and second thin-film transistors being connected to said first ends of said third and fourth insulated gate transistors, second ends of said current paths of said first and second thin-film transistors being connected to a second power supply, said first thin-film transistor having first and second gates respectively above and below said first channel region, said second thin-film transistor having third and fourth gates respectively above and below said second channel region, said second gate being connected to said gate of said third insulated gate transistor, said fourth gate being connected to said gate of said fourth insulated gate transistor, and said first and third gates being connected to said second power supply.
Claim 2
Dependent Claim
335 words
A semiconductor memory device, using a thin-film transistor as a load, comprising: first and second insulated gate transistors of a first conductivity type each having a current path and a gate, first ends of said current paths of said first and second insulated gate transistors being respectively connected to bit lines, and said gates of said first and second insulated gate transistors being connected to a word line; third and fourth insulated gate transistors of said first conductivity type, each having a current path and a gate, first ends of said current paths of said third and fourth insulated gate transistors being respectively connected to second ends of said current paths of said first and second insulated gate transistors, second ends of said current paths of said third and fourth insulated gate transistors being connected to a first power supply, said gate of said third insulated gate transistor being connected to said second end of said current path of said second insulated gate transistor, and said gate of said fourth insulated gate transistor being connected to said second end of said current path of said first insulated gate transistor; and first and second thin-film transistors of a second conductivity type each having a current path, and respectively having first and second channel regions, first ends of said current paths of said first and second thin-film transistors being connected to said first ends of said third and fourth insulated gate transistors, second ends of said current paths of said first and second thin-film transistors being connected to a second power supply, said first thin-film transistor having first and second gates respectively above and below said first channel region, said second thin-film transistor having third and fourth gates respectively above and below said second channel region, said second gate being connected to said gate of said third insulated gate transistor, said fourth gate being connected to said gate of said fourth insulated gate transistor, and said first and third gates being connected to said second power supply.
Claim 3
Dependent Claim
19 words
A memory device according to claim 1, in which said first and second thin-film transistors are formed of polysilicon.
Claim 4
Dependent Claim
20 words
A memory device according to claim 1, in which said first and second thin-film transistors are formed of amorphous silicon.
Claim 5
Dependent Claim
336 words
A random access memory device, using a thin-film transistor as a load, comprising: first and second insulated gate transistors of a first conductivity type each having a current path and a gate, first ends of said current paths of said first and second insulated gate transistors being respectively connected to bit lines, and said gates of said first and second insulated gate transistors being connected to a word line; third and fourth insulated gate transistors of said first conductivity type, each having a current path and a gate, first ends of said current paths of said third and fourth insulated gate transistors being respectively connected to second ends of said current paths of said first and second insulated gate transistors, second ends of said current paths of said third and fourth insulated gate transistors being connected to a first power supply, said gate of said third insulated gate transistor being connected to said second end of said current path of said second insulated gate transistor, and said gates of said fourth insulated gate transistor being connected to said second end of said current path of said first insulated gate transistor; and first and second thin-film transistors of a second conductivity type each having a current path, and respectively having first and second channel regions, first ends of said current paths of said first and second thin-film transistors being connected to said first ends of said third and fourth insulated gate transistors, second ends of said current paths of said first and second thin-film transistors being connected to a second power supply, said first thin-film transistor having first and second gates respectively above and below said first channel region, said second thin-film transistor having third and fourth gates respectively above and below said second channel region, said second gate being connected to said gate of said third insulated gate transistor, said fourth gate being connected to said gate of said fourth insulated gate transistor, and said first and third gates being connected to said second power supply.
Claim 6
Dependent Claim
336 words
A random access memory device, using a thin-film transistor as a load, comprising: first and second insulated gate transistors of a first conductivity type each having a current path and a gate, first ends of said current paths of said first and second insulated gate transistors being respectively connected to bit lines, and said gates of said first and second insulated gate transistors being connected to a word line; third and fourth insulated gate transistors of said first conductivity type, each having a current path and a gate, first ends of said current paths of said third and fourth insulated gate transistors being respectively connected to second ends of said current paths of said first and second insulated gate transistors, second ends of said current paths of said third and fourth insulated gate transistors being connected to a first power supply, said gate of said third insulated gate transistor being connected to said second end of said current path of said second insulated gate transistor, and said gates of said fourth insulated gate transistor being connected to said second end of said current path of said first insulated gate transistor; and first and second thin-film transistors of a second conductivity type each having a current path, and respectively having first and second channel regions, first ends of said current paths of said first and second thin-film transistors being connected to said first ends of said third and fourth insulated gate transistors, second ends of said current paths of said first and second thin-film transistors being connected to a second power supply, said first thin-film transistor having first and second gates respectively above and below said first channel region, said second thin-film transistor having third and fourth gates respectively above and below said second channel region, said second gate being connected to said gate of said third insulated gate transistor, said fourth gate being connected to said gate of said fourth insulated gate transistor, and said first and third gates being connected to said second power supply.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |