Patent US5280452A successfully refreshed from Google Patents.
US5280452A
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Power saving semsing circuits for dynamic random access memory
Assignee: International Business Machines Corp
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Filing: 1991-07-12
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Granted: 1994-01-18
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Expires: 2011-07-12
Abstract
Abstract A sensing circuit for a dynamic random access memory structure is disclosed having first and second bit lines, one of the bit lines being a reference bit line which is held at a precharge voltage when a sense amplifier in the sensing circuit is latched, the sense amplifier includes first and second nodes and first, second, third and fourth transistor devices, the first and second transistor devices form an N-device cross-coupled pair and the third and fourth transistor devices form a P-device cross-coupled pair. The first node is connected to the first bit line and to the second and fourth transistor devices, and the second node is connected to the first and third transistor devices. A first isolation transistor device is connected to the first bit line and a second isolation transistor device is connected to the second bit line. A first clock signal line is connected to the first isolation transistor device and a second clock signal line is connected to the second isolation transistor device. A first equalization transistor device is connected to the first bit line and a second equalization transistor device is connected to the second bit line, a voltage signal line having a voltage value V EQ thereon is connected to the first and second equalization transistor devices, and a third clock signal line is connected to the first equalization device. A fourth clock signal line is connected to the second equalization transistor device, a fifth clock signal line is connected to the first and second N devices, a sixth clock signal line is connected to the third and fourth P devices. The first, second, third, fourth and fifth and sixth clock signal lines have clock signals thereon which occur during a time sequence for precharging the first and second nodes to a precharge voltage value V EQ .
Inventors
- 👤 Sang H. Dhong
- 👤 Lewis M. Terman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
332 words
A sensing circuit for a dynamic random access memory structure comprising: first and second bit lines; a sense amplifier including first and second nodes and first, second, third and fourth transistor devices, said first and second transistor devices forming an N-device cross-coupled pair and said third and fourth transistor devices forming a P-device cross-coupled pair, wherein said first node is connected to said first bit line and to said second and fourth transistor devices, and said second node is connected to said second bit line and said first and third transistor devices; a first isolation transistor device connected to said first bit line and a second isolation transistor device connected to said second bit line; a first clock signal line connected to said first isolation transistor device and a second clock signal line connected to said second isolation transistor device; a first equalization transistor device connected to said first bit line and a second equalization transistor device is connected to said second bit line; a voltage signal line having a precharge voltage value V EQ thereon connected to said first and second equalization transistor devices; a third clock signal line connected to said first equalization transistor device; a fourth clock signal line connected to said second equalization transistor device; a fifth clock signal line connected to said first and second N devices; a sixth clock signal line connected to said third and fourth P devices; said first, second, third, fourth and fifth and sixth clock signal lines being characterized in having clock signals thereon which occur during a time sequence for precharging said first and second nodes to said precharge voltage value V EQ , wherein said sense amplifier is sensed and rewritten by signals occurring in sequence on said fifth and sixth clock signal lines, and wherein said first and second equalization devices and said clock signals on said third and fourth clock signal lines function to maintain one of said first and second bit lines at a constant voltage level.
Claim 2
Dependent Claim
332 words
A sensing circuit for a dynamic random access memory structure comprising: first and second bit lines; a sense amplifier including first and second nodes and first, second, third and fourth transistor devices, said first and second transistor devices forming an N-device cross-coupled pair and said third and fourth transistor devices forming a P-device cross-coupled pair, wherein said first node is connected to said first bit line and to said second and fourth transistor devices, and said second node is connected to said second bit line and said first and third transistor devices; a first isolation transistor device connected to said first bit line and a second isolation transistor device connected to said second bit line; a first clock signal line connected to said first isolation transistor device and a second clock signal line connected to said second isolation transistor device; a first equalization transistor device connected to said first bit line and a second equalization transistor device is connected to said second bit line; a voltage signal line having a precharge voltage value V EQ thereon connected to said first and second equalization transistor devices; a third clock signal line connected to said first equalization transistor device; a fourth clock signal line connected to said second equalization transistor device; a fifth clock signal line connected to said first and second N devices; a sixth clock signal line connected to said third and fourth P devices; said first, second, third, fourth and fifth and sixth clock signal lines being characterized in having clock signals thereon which occur during a time sequence for precharging said first and second nodes to said precharge voltage value V EQ , wherein said sense amplifier is sensed and rewritten by signals occurring in sequence on said fifth and sixth clock signal lines, and wherein said first and second equalization devices and said clock signals on said third and fourth clock signal lines function to maintain one of said first and second bit lines at a constant voltage level.
Claim 3
Dependent Claim
37 words
A sensing circuit for a dynamic random access memory structure according to claim 1 wherein said precharge voltage value V EQ is substantially equal to 1/2 V DD where V DD is the system voltage supply value.
Claim 4
Dependent Claim
135 words
A sensing circuit for a dynamic random access memory structure according to claim 1 wherein said clock signal on one of said third and fourth clock signal lines turns off said one of said first and second equalization transistor devices connected thereto to disconnect one of said first and second bit lines connected thereto from said voltage signal line having said V EQ voltage value thereon, said clock signal on said other one of said third and fourth clock signal lines maintains said other one of said first and second equalization transistor devices on to keep said other one of said first and second bit lines connected to said voltage line having said V EQ voltage value thereon to maintain said other one of said first and second bit lines at said constant voltage level.
Claim 5
Dependent Claim
108 words
A sensing circuit for a dynamic random access memory structure according to claim 1 further including a memory word line connected to an access transistor device, said access transistor device also being connected between a memory cell capacitor and one of said first and second bit lines, wherein a signal on said word line turns on said access transistor device to thereby connect said cell capacitor to charge the voltage level in said one of said first and second bit lines, causing said associated one of said first and second nodes to change voltage level value and produce a voltage level difference between said first and second nodes.
Claim 6
Dependent Claim
49 words
A sensing circuit for a dynamic random access memory structure according to claim 4 wherein said voltage signal levels on said first and second clock signal lines decrease and turn said first and second isolation transistor off, thereby isolating said first and second bit lines from said sense amplifier.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-17 | 1997-07-19 | 1998-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-17 | 2001-07-19 | 2002-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-17 | 2005-07-19 | 2006-01-18 | $7700.00 | Window Closed / Lapsed |