Abstract A semiconductor memory device of a type comprising a plurality of sense amplifiers of differential type arranged in one direction, a pair of bit lines extending outwardly from opposite sides of each of the sense amplifiers, a plurality of word lines extending in a direction intersecting the bit lines, and a memory cell disposed at each of intersecting points between the bit lines and the word lines. The device is characterized in that the memory cells which are connected respectively with the neighboring bit lines are connected with the different word lines. Therefore, not only can the interference noise between each bit-line pair be reduced, but also any possible erroneous operation can be eliminated, thereby increasing the data reading speed.
Inventors
👤 Yasushi Kubota
👤 Katsuji Iguchi
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-23 03:09
CPC Classifications
G; G11; G11C; G11C13/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
88 words
A semiconductor memory device which comprises a plurality of sense amplifiers of differential type arranged in one direction, a pair of bit lines extending outwardly from opposite sides of each of the sense amplifiers, a plurality of word lines extending in a direction intersecting the bit lines, and a memory cell disposed at the intersecting points between the bit lines and the word lines, such that said memory cells that are connected with the neighboring bit lines of a said pair are connected with the different word lines.
Claim 2
Dependent Claim
88 words
A semiconductor memory device which comprises a plurality of sense amplifiers of differential type arranged in one direction, a pair of bit lines extending outwardly from opposite sides of each of the sense amplifiers, a plurality of word lines extending in a direction intersecting the bit lines, and a memory cell disposed at the intersecting points between the bit lines and the word lines, such that said memory cells that are connected with the neighboring bit lines of a said pair are connected with the different word lines.
Claim 3
Dependent Claim
45 words
The semiconductor memory device as claimed in claim 1, further comprising switches connected with bit-line selection lines disposed between the sense amplifiers and the associated bit lines, each of the switches connected with the neighboring bit lines being connected with the different bit-line selection lines.
Claim 4
Dependent Claim
35 words
The semiconductor memory device as claimed in claim 1, wherein the sense amplifiers are arranged in a plurality of rows with the neighboring bit lines extending outwardly from the sense amplifiers in the neighboring rows.