Programmable memory device having reduced power consumption upon unselection

Claim 2

A memory device comprising electrically programmable memory elements, a selection circuit for selecting one of said memory elements, an output circuit having an output terminal for outputting information from the selected memory element, said memory device being of the type in which a selected memory element may be programmed by the application of a programming signal to said output terminal, the inprovement comprising: detection means for detecting an application of said programming signal to said output terminal, and activation means responsive to a detection output of said detection means indicating detection of said programming signal for activating said selection circuit without activating said output circuit.

Claim 3

A memory device according to claim 1, wherein said activation means includes a power supply control circuit for supplying electric power to said selection circuit when activated, and said power supply control circuit is activated in response to said detection output of said detection means.

Claim 4

A memory device according to claim 1, wherein said activation means activates said selection circuit by effecting power supply to said selection circuit in response to the detection output of said detention means.

Claim 5

A memory device comprising a signal input terminal, a memory section including a plurality of memory elements, a selection circuit section for selecting a predetermined one of said memory elements, an output circuit having an output terminal for reading out information from said selected memory element, means for activating and inactivating said output circuit in response to a signal applied to said signal input terminal, power supply control means for controllably supplying an electric power to said selection circuit section when activated, said power supply control means being adapted to be inactivated when said output circuit is inactivated, and a write circuit for applying a write signal supplied from said output terminal to said memory section for programming a memory element selected by said selection circuit section, the improvement comprising: detection means for detecting said write signal at said output terminal, and activation means for activating said power supply control means in response to a detection output of said detection means indicating the detection of said write signal while said output circuit is kept inactivated.

Claim 6

A memory device comprising a signal input terminal, a memory section including a plurality of memory elements, a selection circuit section for selecting a predetermined one of said memory elements, an output circuit having an output terminal for reading out information from said selected memory element, means for activating and inactivating said output circuit in response to a signal applied to said signal input terminal, power supply control means for controllably supplying an electric power to said selection circuit section when activated, said power supply control means being adapted to be inactivated when said output circuit is inactivated, and a write circuit for applying a write signal supplied from said output terminal to said memory section for programming a memory element selected by said selection circuit section, the improvement comprising: detection means for detecting said write signal at said output terminal, and activation means for activating said power supply control means in response to a detection output of said detection means indicating the detection of said write signal while said output circuit is kept inactivated.

Claim 7

A memory device according to claim 4, wherein said detection means includes: a first transistor of one conductivity type having an emitter, base and collector, said emitter being connected to said output terminal, a second transistor of the opposite conductivity type having an emitter, base and collector, said second transistor collector and base being connected respectively to said base and collector of said first transistor, and a diode connected between the collector and base of said second transistor.

Claim 8

A memory device comprising a plurality of memory elements, a selection circuit for selecting said memory elements, means for inactivating said selection circuit, and an output terminal for providing output signals representing information stored in said memory elements, said output signals having at least two possible levels, the improvement comprising: detection means coupled to said output terminal for detecting at said output terminal a signal having a level different from either of said two possible levels and for generating a detection means output signal in response to the detection of said signal having a level different from either of said two possible levels, and activating means responsive to said detection means output signal for activating said selection circuit.

Claim 9

A memory device comprising a plurality of memory elements, a selection circuit for selecting said memory elements, means for inactivating said selection circuit, and an output terminal for providing output signals representing information stored in said memory elements, said output signals having at least two possible levels, the improvement comprising: detection means coupled to said output terminal for detecting at said output terminal a signal having a level different from either of said two possible levels and for generating a detection means output signal in response to the detection of said signal having a level different from either of said two possible levels, and activating means responsive to said detection means output signal for activating said selection circuit.

Claim 10

A memory device according to claim 6, wherein said memory device includes at least one enabling terminal and an output circuit for driving said output terminal in accordance with information stored in said memory elements, and wherein said inactivating means inactivates both said selection circuit and said output circuit in response to said unselect signal at said enabling terminal, said activating means being responsive to said detection means for activating said selection circuit even during the presence of said unselect signal at said enabling terminal.

Claim 11

A memory device according to claim 7, wherein said output circuit remains inactivated when said selection circuit is activated by said activating means during the presence of said unselect signal.

Claim 12

A memory device according to claim 8, said memory device being of the type having means for programming selected memory elements in response to the application of a programming signal to said output terminal, said activating means activating said selection circuit in response to the detection of said programming signal at said output terminal.

Claim 13

A memory device according to claim 7, including a plurality of enabling terminals and a plurality of output circuits and corresponding output terminals, all of said output circuits being inactivated in response to an unselect signal at any one of said enabling terminals, said selection circuit being activated by said activating means in response to detection of said different level signal at any one of said output terminals.