US5276852A
Expired / Lapsed
US
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Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-03-15
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Granted: 1994-01-04
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Expires: 2013-03-15
Abstract
Abstract A CPU module has a processor, cache memory, cache controller, and system interface attached to a processor bus. The system interface is attached to a system bus shared by memory, I/O, and other CPU modules. The cache controller requests control of the processor bus from the processor, and grants control to the system interface. The system interface uses the processor bus to store fill data obtained from memory into the cache in response to a read miss. The system interface also monitors system bus traffic and forwards the addresses of cache blocks to be invalidated to the cache controller over an invalidate bus. The cache controller requests control of the processor bus during a read miss to perform invalidates and writebacks. The processor grants control to the cache controller before the read miss completes, enabling the cache controller to proceed, and then re-issues the read. A protocol between the cache controller and the system interface ensures that cache fills, invalidates, and writebacks are done in the correct order to maintain data coherency. As part of this protocol, the cache controller decides when the system interface may proceed with a fill, and grants the processor bus to the system interface accordingly.
Inventors
- 👤 Michael A. Callander
- 👤 Douglas E. Sanders
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:51
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
129 words
An apparatus to control a write-back cache, comprising: a processor bus; a system interface connected to said processor bus; a processor connected to said processor bus; a cache memory connected to said processor bus; a cache controller connected to said processor bus; first request means for said cache controller to request from said processor control of said processor bus; means for said processor to grant control of said processor bus to said cache controller; second request means for said system interface to request control of said processor bus from said cache controller; and means, responsive to said second request means, for said cache controller to grant control of said processor bus to said system interface, after said processor has granted control of said processor bus to said cache controller
Claim 2
Independent Claim
129 words
An apparatus to control a write-back cache, comprising: a processor bus; a system interface connected to said processor bus; a processor connected to said processor bus; a cache memory connected to said processor bus; a cache controller connected to said processor bus; first request means for said cache controller to request from said processor control of said processor bus; means for said processor to grant control of said processor bus to said cache controller; second request means for said system interface to request control of said processor bus from said cache controller; and means, responsive to said second request means, for said cache controller to grant control of said processor bus to said system interface, after said processor has granted control of said processor bus to said cache controller
Claim 3
Dependent Claim
24 words
The apparatus as in claim 1 further comprising: means for said cache controller to interruptingly request control of said processor bus from said processor.
Claim 4
Dependent Claim
58 words
The apparatus as in claim 2 wherein said means for said cache controller to interruptingly request control of said processor bus from said processor further comprises: means for said cache controller to assert a retry signal; and means for said processor to give control of said processor bus to said cache controller upon receipt of said retry signal.
Claim 5
Dependent Claim
44 words
The apparatus as in claim 1 further comprising: means for said cache controller to assert said first request means for said cache controller to request control of said processor bus, simultaneously with asserting a retry signal to interruptingly request control of said processor bus.
Claim 6
Dependent Claim
20 words
The apparatus as in claim 1 or claim 4 wherein said first request means further comprises a bus request signal.
Claim 7
Dependent Claim
23 words
The apparatus as in claim 5 wherein said processor responds to said retry signal with higher priority than to said bus request signal.
Claim 8
Independent Claim
187 words
An apparatus to control a write-back cache, comprising: a processor bus; a system interface connected to said processor bus; a processor connected to said processor bus; a cache memory connected to said processor bus; a cache controller connected to said processor bus; first decision means for said cache controller to decide when writebacks and invalidates need to be performed in order to keep a remote one processor of a plurality of procesors communicating via said system bus from stalling; second decision means for said cache controller to decide when cache fills may be performed to said cache memory; means, responsive to said first decision means and to said second decision means, for said cache controller to assert a bus request signal when cache fills may be performed, and for said cache controller to assert said bus request signal and a retry signal when a writeback transaction needs to be performed and when an invalidate transaction needs to be performed; and means for said processor to grant control of said processor bus to said cache controller immediately after receiving both said bus request signal and said retry signal
Claim 9
Independent Claim
187 words
An apparatus to control a write-back cache, comprising: a processor bus; a system interface connected to said processor bus; a processor connected to said processor bus; a cache memory connected to said processor bus; a cache controller connected to said processor bus; first decision means for said cache controller to decide when writebacks and invalidates need to be performed in order to keep a remote one processor of a plurality of procesors communicating via said system bus from stalling; second decision means for said cache controller to decide when cache fills may be performed to said cache memory; means, responsive to said first decision means and to said second decision means, for said cache controller to assert a bus request signal when cache fills may be performed, and for said cache controller to assert said bus request signal and a retry signal when a writeback transaction needs to be performed and when an invalidate transaction needs to be performed; and means for said processor to grant control of said processor bus to said cache controller immediately after receiving both said bus request signal and said retry signal
Claim 10
Independent Claim
123 words
A method for controlling a write-back cache in a system having a system interface, a processor, a cache memory, and a cache controller connected to a processor bus, said method comprising the steps of: requesting control of said processor bus by said cache controller, said request directed to said processor; granting control of said processor bus to said cache controller by said processor; requesting control of said processor bus from said cache controller by said system interface; and granting control of said processor bus to said system interface by said cache controller, in response to said requesting control from said cache controller by said system interface, and after control of said processor bus has been granted to said cache controller by said processor.
Claim 11
Independent Claim
123 words
A method for controlling a write-back cache in a system having a system interface, a processor, a cache memory, and a cache controller connected to a processor bus, said method comprising the steps of: requesting control of said processor bus by said cache controller, said request directed to said processor; granting control of said processor bus to said cache controller by said processor; requesting control of said processor bus from said cache controller by said system interface; and granting control of said processor bus to said system interface by said cache controller, in response to said requesting control from said cache controller by said system interface, and after control of said processor bus has been granted to said cache controller by said processor.
Claim 12
Dependent Claim
154 words
A computer system, comprising: a processor bus; a processor connected to said processor bus having means for granting, while not waiting for delivery of read data, control of said processor bus to a requestor asserting a non-interrupting request; a cache memory connected to said processor bus to provide data to said processor in response to a processor read hit; a system interface connected to said processor bus and having means for requesting control of said processor bus to store data in said cache memory in response to a processor read miss, said system interface to be connected to a system bus; a cache controller having means for non-interruptingly requesting from said processor control of said processor bus in response to a processor read miss and means for granting to said system interface control of said processor bus to enable said system interface to store data obtained from said system bus into said cache memory.
Claim 13
Dependent Claim
154 words
A computer system, comprising: a processor bus; a processor connected to said processor bus having means for granting, while not waiting for delivery of read data, control of said processor bus to a requestor asserting a non-interrupting request; a cache memory connected to said processor bus to provide data to said processor in response to a processor read hit; a system interface connected to said processor bus and having means for requesting control of said processor bus to store data in said cache memory in response to a processor read miss, said system interface to be connected to a system bus; a cache controller having means for non-interruptingly requesting from said processor control of said processor bus in response to a processor read miss and means for granting to said system interface control of said processor bus to enable said system interface to store data obtained from said system bus into said cache memory.
Claim 14
Dependent Claim
31 words
A computer system according to claim 9, wherein said non-interrupting request is represented by the assertion of a DMA request signal generated by said cache controller and received by said processor.
Claim 15
Dependent Claim
80 words
A computer system according to claim 9, wherein said processor has means for granting, while waiting for the delivery of read data, control of said processor bus in response to an interrupting request, and wherein said cache controller is connected to said processor bus and has means for interruptingly requesting from said processor control of said processor bus during an interval between a processor read miss and a subsequent request by said system interface for control of said processor bus.
Claim 16
Dependent Claim
36 words
A computer system according to claim 11, wherein said interrupting request is represented by the simultaneous assertion of a retry signal and a DMA request signal generated by said cache controller and received by said processor.
Claim 17
Dependent Claim
73 words
A computer system according to claim 11, further comprising an invalidate bus connected to said cache controller and to said system interface to transfer from said system interface to said cache controller during said interval the addresses of cache blocks to be invalidated, and wherein said cache controller has means for writing back from said cache memory to said system interface dirty ones of those cache blocks to be invalidated during said interval.
Claim 18
Dependent Claim
57 words
A computer system according to claim 9, further comprising an invalidate bus to transfer from said system interface to said cache controller the addresses of cache blocks to be invalidated, and wherein said processor has a primary cache connected to said processor bus to receive from said cache controller the addresses of cache blocks to be invalidated.
Claim 19
Dependent Claim
309 words
A computer system, comprising: a processor bus; an invalidate bus; a processor connected to said processor bus having (i) a primary cache connected to said processor bus; (ii) means for granting, while not waiting for delivery of read data, control of said processor bus in response to a non-interrupting request; and (iii) means for granting, while waiting for the delivery of read data, control of said processor bus in response to an interrupting request; a cache memory connected to said processor bus to provide data to said processor in response to a processor read hit; a system interface connected to said processor bus and to said invalidate bus having (i) means for requesting control of said processor bus to store data in said cache memory in response to a processor read miss; and (ii) means for sending over said invalidate bus the addresses of cache blocks to be invalidated; a cache controller connected to said processor bus and to said invalidate bus to receive from said system interface the addresses of cache blocks to be invalidated, said cache controller having (i) means for non-interruptingly requesting from said processor control of said processor bus in response to a processor read miss; (ii) means for granting to said system interface control of said processor bus to enable said system interface to store data in said cache memory; (iii) means for interruptingly requesting from said processor control of said processor bus during an interval between a processor read miss and a subsequent request by said system interface for control of said processor bus; (iv) means for sending to said primary cache over said processor bus the addresses of cache blocks to be invalidated during said interval; and (v) means for writing back from said cache memory to said system interface dirty ones of those cache blocks to be invalidated during said interval.
Claim 20
Dependent Claim
309 words
A computer system, comprising: a processor bus; an invalidate bus; a processor connected to said processor bus having (i) a primary cache connected to said processor bus; (ii) means for granting, while not waiting for delivery of read data, control of said processor bus in response to a non-interrupting request; and (iii) means for granting, while waiting for the delivery of read data, control of said processor bus in response to an interrupting request; a cache memory connected to said processor bus to provide data to said processor in response to a processor read hit; a system interface connected to said processor bus and to said invalidate bus having (i) means for requesting control of said processor bus to store data in said cache memory in response to a processor read miss; and (ii) means for sending over said invalidate bus the addresses of cache blocks to be invalidated; a cache controller connected to said processor bus and to said invalidate bus to receive from said system interface the addresses of cache blocks to be invalidated, said cache controller having (i) means for non-interruptingly requesting from said processor control of said processor bus in response to a processor read miss; (ii) means for granting to said system interface control of said processor bus to enable said system interface to store data in said cache memory; (iii) means for interruptingly requesting from said processor control of said processor bus during an interval between a processor read miss and a subsequent request by said system interface for control of said processor bus; (iv) means for sending to said primary cache over said processor bus the addresses of cache blocks to be invalidated during said interval; and (v) means for writing back from said cache memory to said system interface dirty ones of those cache blocks to be invalidated during said interval.
Claim 21
Dependent Claim
31 words
A computer system according to claim 15, wherein said non-interrupting request is represented by the assertion of a DMA request signal generated by said cache controller and received by said processor.
Claim 22
Dependent Claim
33 words
A computer system according to claim 15, wherein said interrupting request is represented by the simultaneous assertion of retry and DMA request signals generated by said cache controller and received by said processor.
Claim 23
Independent Claim
99 words
A method of operating a computer system having a processor, cache memory, system interface, and cache controller connected to a processor bus, comprising the steps of: requesting the transfer of control of said processor bus non-interruptingly from said processor to said cache controller when a read miss occurs; transferring control of said processor bus from said processor to said cache controller when a read miss completes; and transferring control of said processor bus from said cache controller to said system interface after a read miss completes to enable said system interface to store fill data in said cache memory.
Claim 24
Independent Claim
99 words
A method of operating a computer system having a processor, cache memory, system interface, and cache controller connected to a processor bus, comprising the steps of: requesting the transfer of control of said processor bus non-interruptingly from said processor to said cache controller when a read miss occurs; transferring control of said processor bus from said processor to said cache controller when a read miss completes; and transferring control of said processor bus from said cache controller to said system interface after a read miss completes to enable said system interface to store fill data in said cache memory.
Claim 25
Dependent Claim
99 words
A method as set forth in claim 18, further comprising the steps of: transferring from said system interface to said cache controller during an interval between a processor read miss and a subsequent request by said system interface for control of said processor bus the addresses of cache blocks to be invalidated; transferring control of said processor bus interruptingly from said processor to said cache controller during said interval; and writing back from said cache memory to said system interface, under the control of said cache controller, dirty ones of those cache blocks to be invalidated during said interval.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-03 | 1997-07-05 | 1998-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-03 | 2001-07-05 | 2002-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-03 | 2005-07-05 | 2006-01-04 | $7700.00 | Window Closed / Lapsed |