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US5258576A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit chip carrier lid

Assignee: Silicon Graphics International Corp
•
Filing: 1992-01-03
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Granted: 1993-11-02
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Expires: 2012-01-03
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Abstract

Abstract A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "opening" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Inventors

  • 👤 Eugene F. Neumann
  • 👤 Melvin C. August
  • 👤 James N. Kruchowski
  • 👤 Stephen Nelson
  • 👤 Richard R. Steitz

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 23:21
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/401; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/641; H10W70/65; H10W72/00; H10W72/701; H10W70/67; H10W70/68; H10W70/682; H10W70/685; H10W90/00; H10W90/701; H10W90/731; H10W90/734

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 82 words
An integrated circuit chip carrier lid for forming a hermetic seal protecting an integrated circuit mounted in a cavity of a chip carrier, comprising: a bottom lip; an inner wall; a glass sealant bonded to said bottom lip and said inner wall such that, when said lid is placed over the cavity of the chip carrier and heated, said glass sealant flows downward from said inner wall of said lid to form a hermetic seal sealing the cavity of the chip carrier.
Claim 2
Dependent Claim 82 words
An integrated circuit chip carrier lid for forming a hermetic seal protecting an integrated circuit mounted in a cavity of a chip carrier, comprising: a bottom lip; an inner wall; a glass sealant bonded to said bottom lip and said inner wall such that, when said lid is placed over the cavity of the chip carrier and heated, said glass sealant flows downward from said inner wall of said lid to form a hermetic seal sealing the cavity of the chip carrier.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-11-01 1997-05-03 1997-11-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-11-01 2001-05-03 2001-11-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-11-01 2005-05-03 2005-11-02 $7700.00 Window Closed / Lapsed

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