Multiple layer, ceramic carrier for high switching speed VLSI chips

Claim 2

In a module for supporting electronic circuit chips in a circuit including a planar ceramic substrate having first and second opposed surfaces; said first surface being adapted for carrying integrated circuit chips, a plurality of electrically conductive strips within said substrate, said strips being juxtaposed with each other and parallel to said surfaces of said substrate, said strips being employed for providing a plurality of electrical interconnections to integrated circuit chips on a first one of said opposed surfaces; a plurality of stacked capacitive elements contained within said substrate, composed of a plurality of laminated thin conductive sheets and a plurality of thin layers of dielectric material; each of said conductive sheets in said stack of capacitive elements being electrically connected to more than one of said plurality of conductive strips by means of coupling conductors distributed along the length of said capacitive elements within said substrate.

Claim 3

A module in accordance with claim 1 wherein said capacitive elements being located within a slot within said substrate with said conductive sheets sandwiched with said dielectric material whereby said conductive sheets form said stacked capacitive elements with each of said conductive sheets having a plurality of tabs extending up to contact said strips, said tabs comprising said conductors.

Claim 4

A module in accordance with claim 2 wherein said conductive sheets are flat, having large parallel surfaces and having edge surfaces, said sheets having high electrical capacitance between adjacent ones thereof and minimal inductive coupling therebetween, with the edge surfaces of said sheets facing outwardly from said slot towards said conductive strips.

Claim 5

A module in accordance with claim 1 wherein each of said coupling conductors is thin and elongated, said conductors being arranged in an array generally within said plane extending into contact with said strips, respectively; said stacked capacitive elements extending parallel to said first and second surfaces of said substrate with each thereof connected to a plurality of said coupling conductors; said thin elongated conductors extending through passages through said stacked capacitive elements with a plurality thereof being in electrical contact with a predetermined one of said capacitive elements at corresponding ones of said passages with a plurality of said conductors in a single plane being connected to the same one of said capacitive elements and the same one of said electrically conductive strips providing a plurality of parallel electrical connections therebetween.

Claim 6

A packaging module for electronic circuit chips including a planar substrate having opposed surfaces; a plurality of stacked power distribution elements; a plurality of land areas on a level adjacent to that of one surface of said substrate for mounting the interconnection to said chips; said stacked power distribution elements being composed of a plurality of parallel, flat sheets having edges and large parallel surfaces with material between said sheets and with high electrical capacitance between said elements and minimal inductive coupling therebetween; with at least one slot extending within said substrate between said opposed surfaces; with said slot containing a stack of said elements extending therethrough with edge surfaces thereof facing outwardly through an opening of said slot and with at least some of said elements insulated electrically from said substrate; the improvement comprising said sheets comprising dielectric material; said material between said sheets comprising a thin film deposit of a metal; with said high electrical capacitance existing between said thin film metal deposits and said substrate comprising a stack of laminated ceramic sheets, a plurality of conductive tabs on the periphery of said thin film metal deposits, a plurality of electrically conductive strips extending across the edges of said stack facing outwardly from said slots with each of said tabs from each one of said thin film deposits connected electrically to a different one of said conductive strips.

Claim 7

A packaging module for electronic circuit chips including a planar substrate having opposed surfaces; a plurality of stacked power distribution elements; a plurality of land areas on a level adjacent to that of one surface of said substrate for mounting the interconnection to said chips; said stacked power distribution elements being composed of a plurality of parallel, flat sheets having edges and large parallel surfaces with material between said sheets and with high electrical capacitance between said elements and minimal inductive coupling therebetween; with at least one slot extending within said substrate between said opposed surfaces; with said slot containing a stack of said elements extending therethrough with edge surfaces thereof facing outwardly through an opening of said slot and with at least some of said elements insulated electrically from said substrate; the improvement comprising said sheets comprising dielectric material; said material between said sheets comprising a thin film deposit of a metal; with said high electrical capacitance existing between said thin film metal deposits and said substrate comprising a stack of laminated ceramic sheets, a plurality of conductive tabs on the periphery of said thin film metal deposits, a plurality of electrically conductive strips extending across the edges of said stack facing outwardly from said slots with each of said tabs from each one of said thin film deposits connected electrically to a different one of said conductive strips.

Claim 8

A module for supporting electronic circuit chips in a circuit including a planar substrate having a first surface adapted for carrying integrated circuit chips, with a plurality of conductive areas serving as pads for electrical and mechanical connections to said chips, the improvement comprising; a capacitor comprising a solid structure having a base surface supported upon said first surface by bonding means, said bonding means providing electrical and mechanical connections to pads upon said first surface, said capacitor including a plurality of alternating layers of stacked laminated thin conductive sheets and a plurality of thin layers of dielectric material; a plurality of conductive strips connected to the base of said capacitor with electrical and mechanical connections to said bonding means; each of said conductive sheets having edge surfaces extending towards said base surface and said first surface with a plurality of tabs on said edge surfaces distributed along the length of said sheet, said tabs extending into electrical contact with different ones of said conductive strips; whereby capacitive coupling between adjacent conductive sheets enhances the capacitive reactance of said module.

Claim 9

A module for supporting electronic circuit chips in a circuit including a planar substrate having a first surface adapted for carrying integrated circuit chips, with a plurality of conductive areas serving as pads for electrical and mechanical connections to said chips, the improvement comprising; a capacitor comprising a solid structure having a base surface supported upon said first surface by bonding means, said bonding means providing electrical and mechanical connections to pads upon said first surface, said capacitor including a plurality of alternating layers of stacked laminated thin conductive sheets and a plurality of thin layers of dielectric material; a plurality of conductive strips connected to the base of said capacitor with electrical and mechanical connections to said bonding means; each of said conductive sheets having edge surfaces extending towards said base surface and said first surface with a plurality of tabs on said edge surfaces distributed along the length of said sheet, said tabs extending into electrical contact with different ones of said conductive strips; whereby capacitive coupling between adjacent conductive sheets enhances the capacitive reactance of said module.

Claim 10

A capacitor comprising a solid structure with a base surface, alternating layers of a plurality of stacked laminated thin conductive sheets and a plurality of thin layers of dielectric material with the planes of said sheets extending towards said base surface; a plurality of conductive strips connected to said base surface of said capacitive element; said conductive sheets having edge surfaces with a plurality of tabs thereon distributed along the length thereof extending into electrical contact with different ones of said conductive strips; whereby said capacitor has high distributed capacitance and low inductance.

Claim 11

A capacitor comprising a solid structure with a base surface, alternating layers of a plurality of stacked laminated thin conductive sheets and a plurality of thin layers of dielectric material with the planes of said sheets extending towards said base surface; a plurality of conductive strips connected to said base surface of said capacitive element; said conductive sheets having edge surfaces with a plurality of tabs thereon distributed along the length thereof extending into electrical contact with different ones of said conductive strips; whereby said capacitor has high distributed capacitance and low inductance.

Claim 12

A stack of capacitive elements composed of thin conductive sheets laminated with thin layers of dielectric material, an array of electrically conductive strips extending in juxtaposition with each other and integrally supported mechanically with said stack of capacitive elements, a plurality of conductors spaced apart connected between individual ones of said conductive sheets and said conductive strips, with each of said capacitive elements being connected to a plurality of said conductors along the length of said capacitive elements to provide a plurality of distributed current paths from said conductive sheets to said conductive strips.

Claim 13

A stack of capacitive elements composed of thin conductive sheets laminated with thin layers of dielectric material, an array of electrically conductive strips extending in juxtaposition with each other and integrally supported mechanically with said stack of capacitive elements, a plurality of conductors spaced apart connected between individual ones of said conductive sheets and said conductive strips, with each of said capacitive elements being connected to a plurality of said conductors along the length of said capacitive elements to provide a plurality of distributed current paths from said conductive sheets to said conductive strips.

Claim 14

A stack in accordance with claim 8 wherein the planes of the sheets are parallel to the planes of strips and said conductors extend through vias in said capacitive sheets with a said strip connected to a said capacitive sheet by a plurality of parallel ones of said conductors.

Claim 15

A stack in accordance with claim 8 wherein the planes of said sheets intersect the planes of said strips, and said conductors extend from the edges of said sheets into contact with said strips with a plurality of said conductors on each of said sheets extending into contact with a plurality of strips.

Claim 16

A stack in accordance with claim 10 wherein said conductors comprise tabs extending from the edge of said conductive sheets.