Method for counting the number of program instruction completed by a microprocessor

Claim 1

A method for debugging computer program instructions executing in a processor in a normal mode of operation, wherein said processor has in addition to the normal mode of operation, an exception mode of operation, a control unit, and a programmable counter and further wherein said control unit generates an instruction complete signal upon completion of each computer program instruction and said programmable counter is responsive to said instruction complete signal, said method comprising the steps of: loading said computer program instructions by said processor so that said processor begins execution of said computer program instructions in said normal mode of operation; reading a value of said programmable counter to obtain a first reading; charging the value of said programmable counter in a selected direction in response to each instruction complete signal from said control unit; reading the value of said programmable counter upon termination of execution of said computer program instructions to obtain a second reading; forming a difference between said first reading and said second reading; reloading said computer program instructions by said processor so that said processor begins execution of said computer program instructions in said normal mode of operation; setting the programmable counter to a first selected number that is less than said difference between said first reading and said second reading; changing the value of said programmable counter in said selected direction in response to each instruction complete signal from said control unit; and forcing a change of mode of operation to the exception mode upon said programmable counter reaching a second selected number.

Claim 2

A method for debugging computer program instructions executing in a processor in a normal mode of operation, wherein said processor has in addition to the normal mode of operation, an exception mode of operation, a control unit, and a programmable counter and further wherein said control unit generates an instruction complete signal upon completion of each computer program instruction and said programmable counter is responsive to said instruction complete signal, said method comprising the steps of: loading said computer program instructions by said processor so that said processor begins execution of said computer program instructions in said normal mode of operation; reading a value of said programmable counter to obtain a first reading; charging the value of said programmable counter in a selected direction in response to each instruction complete signal from said control unit; reading the value of said programmable counter upon termination of execution of said computer program instructions to obtain a second reading; forming a difference between said first reading and said second reading; reloading said computer program instructions by said processor so that said processor begins execution of said computer program instructions in said normal mode of operation; setting the programmable counter to a first selected number that is less than said difference between said first reading and said second reading; changing the value of said programmable counter in said selected direction in response to each instruction complete signal from said control unit; and forcing a change of mode of operation to the exception mode upon said programmable counter reaching a second selected number.

Claim 4

The method claim of 1, wherein said processor has an execution level and further wherein said steps are performed for said execution level of said processor.

Claim 6

A system for executing computer program instructions including: a control register having an execution level bit and a count trap enable bit; a decoder, operatively coupled to said execution level bit in said control register, having an input line coupled to said execution level bit and an output line wherein an output signal on said output line of said decoder has a first level upon said execution level bit being set and a second level otherwise; a control unit having a force exception input line and an instruction complete output line wherein: said control unit has a normal mode of operation and an exception mode of operation; said control unit executes said computer program instructions in said normal mode of operation and upon completion of execution of each computer program instruction generates an instruction complete signal on said instruction complete output line; and said control unit enters said exception mode of operation upon receiving a signal on said force exception input line; a first logic gate having first and second input terminals and an output line wherein: said first input terminal is connected to said decoder output line; said second input terminal is connected to said control unit instruction complete output line; and said first logic gate generates an active signal on said output line in response to said decoder first level signal on said first terminal in combination with an instruction complete signal on said second input terminal; a counter having an input line and an output line wherein: said counter input line is connected to said first logic gate output line; said counter changes value in response to said active output signal of said first logic gate; and said counter generates a signal on said counter output line upon the value of said counter equaling a predetermined value; and a second logic gate having first and second input terminals and an output line wherein: said first input terminal is connected to said count trap enable bit; said second input terminal is connected to said counter output line; and said output line is connected to said force exception line of said control unit wherein said second logic gate generates a signal on said output line of said second logic gate in response to said count trap enable bit being set in combination with said output signal from said counter and in response, to said second logic gate output signal, said control unit enters said exception mode of operation.

Claim 7

A system for executing computer program instructions including: a control register having an execution level bit and a count trap enable bit; a decoder, operatively coupled to said execution level bit in said control register, having an input line coupled to said execution level bit and an output line wherein an output signal on said output line of said decoder has a first level upon said execution level bit being set and a second level otherwise; a control unit having a force exception input line and an instruction complete output line wherein: said control unit has a normal mode of operation and an exception mode of operation; said control unit executes said computer program instructions in said normal mode of operation and upon completion of execution of each computer program instruction generates an instruction complete signal on said instruction complete output line; and said control unit enters said exception mode of operation upon receiving a signal on said force exception input line; a first logic gate having first and second input terminals and an output line wherein: said first input terminal is connected to said decoder output line; said second input terminal is connected to said control unit instruction complete output line; and said first logic gate generates an active signal on said output line in response to said decoder first level signal on said first terminal in combination with an instruction complete signal on said second input terminal; a counter having an input line and an output line wherein: said counter input line is connected to said first logic gate output line; said counter changes value in response to said active output signal of said first logic gate; and said counter generates a signal on said counter output line upon the value of said counter equaling a predetermined value; and a second logic gate having first and second input terminals and an output line wherein: said first input terminal is connected to said count trap enable bit; said second input terminal is connected to said counter output line; and said output line is connected to said force exception line of said control unit wherein said second logic gate generates a signal on said output line of said second logic gate in response to said count trap enable bit being set in combination with said output signal from said counter and in response, to said second logic gate output signal, said control unit enters said exception mode of operation.