Arithmetic operation processing apparatus of the parallel processing type and compiler which is used in this apparatus

Claim 2

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said whole executing sequence, and means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; and data transfer means for transferring necessary operand data and result data relevant to said arithmetic operations between said first processor and said arithmetic operating unit.

Claim 3

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said executing sequence, means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; said second processor including data transfer means for transferring necessary operand data and result data relevant to said arithmetic operations between said first processor and said arithmetic operating unit; wherein said first processor performs data transfer using said data transfer means with said arithmetic operating unit in parallel with the output of an instruction to the arithmetic operating unit from said second processor.

Claim 4

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said executing sequence, means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; said second processor including data transfer means for transferring necessary operand data and result data relevant to said arithmetic operations between said first processor and said arithmetic operating unit; wherein said first processor performs data transfer using said data transfer means with said arithmetic operating unit in parallel with the output of an instruction to the arithmetic operating unit from said second processor.

Claim 5

An apparatus according to claim 2, wherein said data transfer is performed between memory means connected to said first processor and a register file which is provided in said arithmetic operating unit.

Claim 6

An apparatus according to claim 3, wherein said first processor includes means for outputting an instruction for controlling said arithmetic operating unit to execute an arithmetic operation, and further including first switching means for receiving instructions from both of said second and first processors and for selectively supplying one of said instructions to the arithmetic operating unit.

Claim 7

An apparatus according to claim 4, wherein said second processor has a data input/output function, and further including second switching means for enabling a transfer of said data either between the first processor and the arithmetic operating unit or between the second processor and the arithmetic operating unit by selectively connecting one of said first and second processors to said arithmetic operating unit.

Claim 8

An apparatus according to claim 2, wherein said second processor has a data input/output function, and further including second switching means for enabling a transfer of said data either between the first processor and the arithmetic operating unit or between the second processor and the arithmetic operating unit by selectively connecting one of said first and second processors to said arithmetic operating unit.

Claim 9

An apparatus according to claim 6, wherein said data transfer between the second processor and the arithmetic operating unit is performed between a local memory provided in the second processor and a register file provided in the arithmetic operating unit.

Claim 10

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said whole executing sequence, and means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; and first switching means for receiving instructions from both of said second and first processors for selectively supplying one of said instructions to the arithmetic operating unit; wherein said first and second processors have the same machine instruction set for controlling said arithmetic operating unit to execute arithmetic operations and are performed for said arithmetic operating unit in obedience to said machine instruction set.

Claim 11

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said whole executing sequence, and means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; and first switching means for receiving instructions from both of said second and first processors for selectively supplying one of said instructions to the arithmetic operating unit; wherein said first and second processors have the same machine instruction set for controlling said arithmetic operating unit to execute arithmetic operations and are performed for said arithmetic operating unit in obedience to said machine instruction set.

Claim 12

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said whole executing sequence, and means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; wherein at least one macro instruction designates at least one instruction which is continuously executed.

Claim 13

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said whole executing sequence, and means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; wherein at least one macro instruction designates at least one instruction which is continuously executed.

Claim 14

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said whole executing sequence, and means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; wherein the instruction constituting a macro instruction and said macro instruction are stored as machine language into said first processor.

Claim 15

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said whole executing sequence, and means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; wherein the instruction constituting a macro instruction and said macro instruction are stored as machine language into said first processor.

Claim 16

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said whole executing sequence, and means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; wherein said first processor has means for indicating a macro instruction sequence representative of a number of instructions to be executed by the arithmetic operating unit, and said second processor has means for latching a number of instructions indicated by said second processor and counting a number of arithmetic operating instructions for making the second processor operative each time an instruction is executed by the arithmetic operating unit until the macro instruction coincides with the number of instructions indicated and means for stopping the operation of the first processor when the execution of the macro instruction sequence which is being executed is finished if a next macro instruction is indicated from the first processor while the second processor is operating.

Claim 17

An arithmetic operation processing apparatus of a parallel processing type, comprising: a first processor having means for outputting a series of macro instruction sequences which are each obtained by dividing a whole executing sequence composed of multiple instructions to specify respective arithmetic operating processes; a second processor connected to receive said series of macro instruction sequences from said first processor and including means for storing said multiple instructions of said whole executing sequence, and means coupled to said storing means for outputting instructions relevant to an arithmetic operating process of a macro instruction sequence in response to the receipt of each macro instruction; an arithmetic operating unit for executing an arithmetic operation on data in accordance with an instruction received from said second processor; wherein said first processor has means for indicating a macro instruction sequence representative of a number of instructions to be executed by the arithmetic operating unit, and said second processor has means for latching a number of instructions indicated by said second processor and counting a number of arithmetic operating instructions for making the second processor operative each time an instruction is executed by the arithmetic operating unit until the macro instruction coincides with the number of instructions indicated and means for stopping the operation of the first processor when the execution of the macro instruction sequence which is being executed is finished if a next macro instruction is indicated from the first processor while the second processor is operating.

Claim 18

A parallel arithmetic operating type system for use as an arithmetic operation processing apparatus of a parallel processing type, comprising: an arithmetic operation processing unit to perform arithmetic operating processes on the basis of instructions; a first processor having means which divides a whole arithmetic operation processing sequence of instructions to be executed by said arithmetic operation processing unit into a macro sequences corresponding to macro instructions received from outside of said first processor and sets these macro sequences as macro instruction steps, and which indicates the instructions forming each macro instruction step one by one along a macro instruction sequence basis to the arithmetic operation processing unit in response to a macro instruction, and which is returned to a waiting mode of a next macro instruction after completion of the indication of the instructions included in a relevant macro instruction steps if there is no macro instruction from the outside; a second processor having means for controlling the whole arithmetic operating sequence replaced to a plurality of macro instruction steps and for generating macro instructions to said first processor, said second processor including means for performing a transfer process of data with said arithmetic operation processing unit in parallel with the operations of at least the arithmetic operation processing unit and the first processor; data transfer means for transferring necessary operand data and result data relevant to said arithmetic operations between said second processor and said arithmetic operation processing unit; and a compiler having object program generating means for combining the arithmetic operation processing sequence described as compiling means of a compiler system to describe the arithmetic operation processing sequence of the arithmetic operation processing unit to a plurality of macro sequences consisting of one or more instructions upon compiling along said processing sequence, for defining each of said plurality of macro sequences as a macro instruction step, for assigning said macro instruction steps to the first processor, for assigning the data transfer processing and the generating operation of each macro instruction output for the first processor to the second processor, during the execution of the nth macro instruction step by the first processor, for enabling said second processor to transfer of said data, which will be necessary by the second processor in a subsequent macro instruction step, or resultant data processed in a preceding macro instruction step, in parallel between a memory system provided for the second processor and the arithmetic operation processing unit.

Claim 19

A parallel arithmetic operating type system for use as an arithmetic operation processing apparatus of a parallel processing type, comprising: an arithmetic operation processing unit to perform arithmetic operating processes on the basis of instructions; a first processor having means which divides a whole arithmetic operation processing sequence of instructions to be executed by said arithmetic operation processing unit into a macro sequences corresponding to macro instructions received from outside of said first processor and sets these macro sequences as macro instruction steps, and which indicates the instructions forming each macro instruction step one by one along a macro instruction sequence basis to the arithmetic operation processing unit in response to a macro instruction, and which is returned to a waiting mode of a next macro instruction after completion of the indication of the instructions included in a relevant macro instruction steps if there is no macro instruction from the outside; a second processor having means for controlling the whole arithmetic operating sequence replaced to a plurality of macro instruction steps and for generating macro instructions to said first processor, said second processor including means for performing a transfer process of data with said arithmetic operation processing unit in parallel with the operations of at least the arithmetic operation processing unit and the first processor; data transfer means for transferring necessary operand data and result data relevant to said arithmetic operations between said second processor and said arithmetic operation processing unit; and a compiler having object program generating means for combining the arithmetic operation processing sequence described as compiling means of a compiler system to describe the arithmetic operation processing sequence of the arithmetic operation processing unit to a plurality of macro sequences consisting of one or more instructions upon compiling along said processing sequence, for defining each of said plurality of macro sequences as a macro instruction step, for assigning said macro instruction steps to the first processor, for assigning the data transfer processing and the generating operation of each macro instruction output for the first processor to the second processor, during the execution of the nth macro instruction step by the first processor, for enabling said second processor to transfer of said data, which will be necessary by the second processor in a subsequent macro instruction step, or resultant data processed in a preceding macro instruction step, in parallel between a memory system provided for the second processor and the arithmetic operation processing unit.

Claim 20

A system according to claim 12, further including means for compiling loop arithmetic operations, comprising a compiling system which develops loop processes to object programs in a manner such that the series of arithmetic operating processes in a loop are regarded as the macro sequences and defined to the macro instruction steps and assigned to the first processor, the data transfer processing and the generating operation of the macro instruction to the first processor are assigned to the second processor, and during the execution of the macro instruction step of the nth loop by the second processor, there is executed in parallel therewith the process to transfer data, which will be necessary by the second processor in the macro instruction steps of the (n+1)th and subsequent loops, or the resultant data processed by the (n-1)th and preceding macro instruction steps between the memory system provided for the second processor and the arithmetic operation processing unit.