US5252846A
Expired / Lapsed
US
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Semiconductor memory device with an improved erroneous write characteristic and erasure characteristic
Assignee: Toshiba Corp
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Filing: 1992-07-07
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Granted: 1993-10-12
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Expires: 2012-07-07
Abstract
Abstract A semiconductor memory device containing a number of memory cells each having a floating gate, an erase gate, and a control gate. In a data erasure mode, electrons are discharged from the floating gate into the erase gate. In the semiconductor memory device, an impurity concentration in at least a region of the floating gate overlapping with the erase gate is lower than that of the erase gate.
Inventors
- 👤 Shinichi Tanaka
- 👤 Masayuki Hori
- 👤 Kazunori Kanebako
- 👤 Noriyoshi Tozawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
131 words
A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a floating gate containing an impurity at a predetermined concentration and layered on a first insulating film which is also layered on said substrate; an erase gate layered above said flowing gate, with a second insulating film interlaid therebetween, a part of said erase gate overlapping with said floating gate, and said erase gate containing impurity at a predetermined concentration; and a control gate layered above said floating gate and said erase gate, including said part of said erase gate overlapping with said floating gate, with a third insulating film interlaid therebetween; wherein an impurity concentration in at least a part of said floating gate overlapping with the erase gate is lower than that of said erase gate.
Claim 2
Dependent Claim
131 words
A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a floating gate containing an impurity at a predetermined concentration and layered on a first insulating film which is also layered on said substrate; an erase gate layered above said flowing gate, with a second insulating film interlaid therebetween, a part of said erase gate overlapping with said floating gate, and said erase gate containing impurity at a predetermined concentration; and a control gate layered above said floating gate and said erase gate, including said part of said erase gate overlapping with said floating gate, with a third insulating film interlaid therebetween; wherein an impurity concentration in at least a part of said floating gate overlapping with the erase gate is lower than that of said erase gate.
Claim 3
Dependent Claim
42 words
A semiconductor memory device according to claim 1, wherein the impurity concentration in said erase gate is 6×10 20 /cm 3 or more, and the impurity concentration in said part of said floating gate is less than 6×10 20 /cm 3 .
Claim 4
Dependent Claim
42 words
A semiconductor memory device according to claim 1, wherein the impurity concentration in said erase gate is 6×10 20 /cm 3 or more, and the impurity concentration in the whole of said floating gate is less than 6×10 20 /cm 3 .
Claim 5
Dependent Claim
44 words
A semiconductor memory device according to claim 1, wherein said floating gate, said erase gate, and said control gate are made of polysilicon, and the impurity contained in said floating gate and said erase gate, and an impurity in said control gate is phosphorus.
Claim 6
Dependent Claim
44 words
A semiconductor memory device according to claim 1, wherein said floating gate, said erase gate, and said control gate are made of polysilicon, and the impurity contained in said floating gate and said erase gate, and an impurity in said control gate is arsenic.
Claim 7
Dependent Claim
40 words
A semiconductor memory device according to claim 1, wherein an insulating film having a three-layered structure consisting of a first oxide film, a nitride film, and a second oxide film is interlaid between said erase gate and said control gate.
Claim 8
Dependent Claim
25 words
A semiconductor memory device according to claim 1, wherein said control gate is laid over said erase gate, with said third insulating film interlaid therebetween.
Claim 9
Dependent Claim
31 words
A semiconductor memory device according to claim 1, wherein said third insulating film has a three-layered structure consisting of a first oxide film, a nitride film and a second oxide film.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-10-11 | 1997-04-12 | 1997-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-11 | 2001-04-12 | 2001-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-11 | 2005-04-12 | 2005-10-12 | $7700.00 | Window Closed / Lapsed |