← Back to Patent Explorer
EP0282022A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Toshiba Corp
•
Filing: 1988-03-09
•
Granted: —
•
Expires: 2008-03-09
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Disclosed is a semiconductor memory device con­taining a number of memory cells each having a floating gate (13), an erase gate (15), and a control gate (17). In a data erasure mode, electrons are discharged from the floating gate (13) into the erase gate electrode (15). In the semiconductor memory device, an insulating film interlaid between the erase gate (15) and the con­trol gate (17) has a three-layered structure consisting of a silicon oxide film (16A), a silicon nitride film (16B), and a silicon oxide film (16C).

Inventors

  • 👤 Shinichi C/O Patent Division Tanaka
  • 👤 Masayuki C/O Patent Division Hori
  • 👤 Noriyoshi C/O Patent Division Tozawa

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 04:47
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 100 words
A semiconductor memory device, characterized by a semiconductor substrate (10) of a first conduc­tivity type; a floating gate (13) layered on a first insulating film (12) which is also layered on said substrate; an erase gate (15) partially overlapping with said floating gate (13), with a second insulating film (14) interlaid therebetween; and a control gate (17) layered above said floating gate (13) and said erase gate (15), with a third insu­lating film (14, 16) of a three-layered structure con­sisting of a first oxide film, a nitride film, and a second oxide film, said third insulating film being interlaid therebetween.
Claim 2
Dependent Claim 100 words
A semiconductor memory device, characterized by a semiconductor substrate (10) of a first conduc­tivity type; a floating gate (13) layered on a first insulating film (12) which is also layered on said substrate; an erase gate (15) partially overlapping with said floating gate (13), with a second insulating film (14) interlaid therebetween; and a control gate (17) layered above said floating gate (13) and said erase gate (15), with a third insu­lating film (14, 16) of a three-layered structure con­sisting of a first oxide film, a nitride film, and a second oxide film, said third insulating film being interlaid therebetween.
Claim 3
Dependent Claim 44 words
A semiconductor memory device according to claim 1, characterized in that said semiconductor sub­strate (10) is a silicon substrate, and said third insu­lating film has a three-layered structure consisting of a first silicon oxide film, a nitride film, and a second silicon oxide film.
Claim 4
Dependent Claim 42 words
A semiconductor memory device according to claim 2, characterized in that said first silicon oxide film is more than 400 Angstroms in thickness, said nitride film is more than 150 angstroms, and said second silicon oxide film is more than 50 Angstroms.
Claim 5
Dependent Claim 32 words
A semiconductor memory device according to claim 1, characterized in that said floating gate (13), said erase gate (15), and said control gate (17) are made of polysilicon, and contain an impurity.
Claim 6
Dependent Claim 28 words
A semiconductor memory device according to claim 4, characterized in that an impurity concentration of said floating gate (13) is lower than that of said erase gate (15).
Claim 7
Dependent Claim 46 words
A semiconductor memory device according to claim 4, characterized in that impurity concentrations contained in said erase gate (15) and said control gate (17) are approximately equal to its solution limit, and impurity concentration contained in said floating gate (13) is less than the solution limit.
Claim 8
Dependent Claim 44 words
A semiconductor memory device according to claim 6, characterized in that an impurity concentra­tion of said erase gate (15) and said control gate is 6 × 10²⁰/cm³ or more, and an impurity concentration of said floating gate (13) is less than 6 × 10²⁰/cm³.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag