US5250837A
Expired / Lapsed
US
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Method for dielectrically isolating integrated circuits using doped oxide sidewalls
Assignee: Delphi Technologies Inc
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Filing: 1992-08-31
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Granted: 1993-10-05
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Expires: 2012-08-31
Abstract
Abstract A method for dielectrically isolating a semiconductor integrated circuit is provided. Each integrated circuit is substantially surrounded by silicon oxide sidewalls which have been appropriately doped to be of an opposite conductivity type as the surrounding substrate. The doped silicon oxide sidewalls are formed prior to the growth of epitaxial silicon within the sidewalls. Upon deposition of the epitaxial silicon the dopant within the oxide sidewalls diffuses into the adjacent epitaxial silicon, thereby resulting in a heavily doped, low resistivity region of epitaxial silicon adjacent to and along the entire length of the oxide sidewall. This heavily doped region results in the substantial elimination of charge-depleting parasitic currents along the sidewalls during use of the integrated circuit. In addition, the heavily doped, low resistivity epitaxial region provides an electrically conductive contact to a buried layer within an integrated circuit having such a buried layer. Extremely thin and long, contacts can be made to the buried layer using this method, without the traditional need for long diffusion times which result in excessively wide diffusion zones.
Inventors
- 👤 Douglas R. Sparks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:59
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/018; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
227 words
A semiconductor integrated circuit comprising: a monocrystalline silicon substrate oriented along a single crystallographic plane of P-type electrical conductivity; a trench-like region in a monocrystalline silicon surface of said monocrystalline silicon substrate, wherein said trench-like region has monocrystalline silicon side walls and a monocrystalline silicon bottom wall; a P-type region in said monocrystalline silicon substrate, which region is substantially coextensive with said trench side walls; a buried layer of N+ type electrical conductivity in said monocrystalline silicon substrate substantially coextensive with the bottom wall of said trench; N-type monocrystalline silicon on said trench bottom wall, effective to contact said buried layer, and extending up from said trench bottom wall to substantially fill said trench; a doped silicon oxide coating on said trench sidewalls, which doped silicon oxide coating contains an N-type conductivity determining impurity and laterally substantially dielectrically isolates said monocrystalline silicon which substantially fills said trench from monocrystalline silicon of said substrate which is coextensive with said trench sidewalls; and a heavily doped N-type diffusion region in said monocrystalline silicon in said trench, which region is adjacent to said doped oxide sidewalls characterized by a dopant level of between about 10 17 atoms; cm 3 and about 10 21 atoms/cm 3 , effective to provide a low electrical resistance path between said buried layer and said surface within said trench and adjacent said doped oxide coating.
Claim 2
Dependent Claim
227 words
A semiconductor integrated circuit comprising: a monocrystalline silicon substrate oriented along a single crystallographic plane of P-type electrical conductivity; a trench-like region in a monocrystalline silicon surface of said monocrystalline silicon substrate, wherein said trench-like region has monocrystalline silicon side walls and a monocrystalline silicon bottom wall; a P-type region in said monocrystalline silicon substrate, which region is substantially coextensive with said trench side walls; a buried layer of N+ type electrical conductivity in said monocrystalline silicon substrate substantially coextensive with the bottom wall of said trench; N-type monocrystalline silicon on said trench bottom wall, effective to contact said buried layer, and extending up from said trench bottom wall to substantially fill said trench; a doped silicon oxide coating on said trench sidewalls, which doped silicon oxide coating contains an N-type conductivity determining impurity and laterally substantially dielectrically isolates said monocrystalline silicon which substantially fills said trench from monocrystalline silicon of said substrate which is coextensive with said trench sidewalls; and a heavily doped N-type diffusion region in said monocrystalline silicon in said trench, which region is adjacent to said doped oxide sidewalls characterized by a dopant level of between about 10 17 atoms; cm 3 and about 10 21 atoms/cm 3 , effective to provide a low electrical resistance path between said buried layer and said surface within said trench and adjacent said doped oxide coating.
Claim 3
Dependent Claim
20 words
A semiconductor integrated circuit device as recited in claim 1 wherein said silicon substrate is oriented along the crystallographic plane.
Claim 4
Dependent Claim
21 words
A semiconductor integrated circuit device as recited in claim 1 wherein said silicon substrate is oriented along the [111] crystallographic plane.
Claim 5
Dependent Claim
123 words
A semiconductor integrated circuit device as recited in claim 1 wherein said monocrystalline silicon substantially filling said trench has an outer surface generally co-planar with said monocrystalline silicon of said substrate surface, a P-type island-like region is inset in said outer surface and spaced from said trench side walls, an N-type island-like region is inset in said outer surface within said P-type island-like region, effective to provide a bipolar transistor in said monocrystalline silicon substantially filling said trench, wherein portions of said monocrystalline silicon substantially filling said trench reduce collector series resistance for said bipolar transistor by providing monocrystalline interior sidewalls that contain an N-type conductivity determining impurity and form a low electrical resistance path between said outer surface and said buried layer.
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| 3.5 Years (Year 4) | 1996-10-04 | 1997-04-05 | 1997-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-04 | 2001-04-05 | 2001-10-05 | $3760.00 | Window Closed / Lapsed |
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