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US4717682A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device with conductive trench sidewalls

Assignee: Toshiba Corp
•
Filing: 1986-02-19
•
Granted: 1988-01-05
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Expires: 2006-02-19
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Abstract

Abstract A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.

Inventors

  • 👤 Shin-ichi Taka
  • 👤 Jiro Ohshima
  • 👤 Masahiro Abe
  • 👤 Masaharu Aoyama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 23:19
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/80; H10D10/821; H10W; H10W20/00; H10W20/01; H10W20/021; H10D10/01

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 147 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a buried region doped with an impurity in a major surface of a semiconductor substrate; (b) forming a epitaxial layer on the major surface of said semiconductor substrate which includes said buried region; (c) forming an annular trench extending through said buried region; (d) depositing impurity-doped polysilicon on an inner surface of said annular trench, saidn impurity being of the same conductivity type as that of said buried region; (d') etching the impurity-doped polysilicon by reactive ion etching to leave as a conductive layer a portion of said impurity-doped polysilicon in direct contact with a side wall surface of said annular trench; (e) filling said annular trench with an insulating material; and (f) forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench.
Claim 2
Independent Claim 147 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a buried region doped with an impurity in a major surface of a semiconductor substrate; (b) forming a epitaxial layer on the major surface of said semiconductor substrate which includes said buried region; (c) forming an annular trench extending through said buried region; (d) depositing impurity-doped polysilicon on an inner surface of said annular trench, saidn impurity being of the same conductivity type as that of said buried region; (d') etching the impurity-doped polysilicon by reactive ion etching to leave as a conductive layer a portion of said impurity-doped polysilicon in direct contact with a side wall surface of said annular trench; (e) filling said annular trench with an insulating material; and (f) forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench.
Claim 3
Dependent Claim 28 words
A method according to claim 1, wherein the step (c) comprises the step of forming an annular trench having a wall surface substantially perpendicular to said semiconductor substrate.
Claim 4
Dependent Claim 16 words
A method according to claim 1, wherein said impurity-doped polysilicon is deposited by chemical vapor deposition.
Claim 5
Dependent Claim 16 words
A method according to claim 1, wherein said impurity-doped polysilicon is deposited by physical vapor deposition.
Claim 6
Dependent Claim 20 words
A method according to claim 1, wherein said functional element formed in the step (f) is a bipolar semiconductor device.

References Cited (Backward Citations)

US3947299A Cited
US4140558A Cited
US4322883A Cited
US4488162A Cited
US4383883A Cited
US4459325A Cited
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US4619037A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-01-04 1991-07-06 1992-01-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-01-04 1995-07-06 1996-01-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-01-04 1999-07-06 2000-01-05 $7700.00 Window Closed / Lapsed

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