Integrated CMOS gate-array circuit

Claim 1

An integrated CMOS circuit of the gate array type having a semiconductor body provided at a surface and comprising: a first row and an adjacent parallel second row of n-channel MOS transistors having common gate electrodes in the form of conductor tracks extending transverse to the row direction over both rows; a first row and an adjacent parallel second row of p-channel MOS transistors having common gate electrodes in the form of conductor tracks extending transverse to the row direction over both rows; characterized in that between the first and second rows of n-channel transistors and between the first and second rows of p-channel transistors, respectively, at least one further row of n-channel transistors and at least one further row of p-channel transistors, respectively, is provided, which extend parallel to the first and second rows, the gate electrodes of the first and second rows of n-channel transistors constituting gate electrodes of the at least one further row of n-channel transistors and the gate electrodes of the first and second rows of p-channel transistors constituting gate electrodes of the at least one further row of p-channel transistors, while the transistors of the at least one further row of n-channel transistors and p-channel transistors, respectively, have a width which is at least three times the width of the transistors of the first and second rows of n-channel transistors and p-channel transistors, respectively, the width of the transistors of the first and second rows of n-channel transistors being equal, and the width of the transistors of the first and second rows of p-channel transistors being equal.