EP0336741A2
Expired / Lapsed
EP
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Semiconductor integrated circuit with bipolar transistors and MOSFETs
Assignee: Hitachi Ltd
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Filing: 1989-04-05
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Granted: —
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Expires: 2009-04-05
Abstract
Abstract A logic circuit forming a gate array is designed depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermined value and a second Bi-CMOS circuit including an output bipolar transistor whose emitter size is larger than the emitter size of the output bipolar transistor of the first Bi-CMOS circuit. In this way, the logic circuit is brought into a circuit form whose output load capacitance can be charged and discharged fastest. As a result, the logic circuit constructed in the gate array by adopting the design technique as stated above has its operating speed raised.
Inventors
- 👤 Shuuichi Miyaoka
- 👤 Masanori Odaka
- 👤 Katsumi Ogiue
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 16:15
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H10D84/01; H10D84/0107; H10D84/0109; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/90; H10D84/996; H10W; H10W15/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
123 words
A semiconductor integrated circuit comprising: a semiconductor substrate (100) which has a principal surface; and a plurality of basic cells (BC) which are on the principal surface and each of which includes a pair of bipolar transistors and a plurality of MOSFETs; characterised in that: the basic cells (BC) are arranged in a predetermined pattern on the substrate (100), which predetermined pattern is such that said pair of bipolar transistors included in one of said basic cells are arranged near a certain latus of said one basic cell, and wherein said pair of bipolar transistors included in the other basic cell are arranged in mirror symmetry to said pair of bipolar transistors of said one basic cell with respect to said certain latus.
Claim 2
Dependent Claim
123 words
A semiconductor integrated circuit comprising: a semiconductor substrate (100) which has a principal surface; and a plurality of basic cells (BC) which are on the principal surface and each of which includes a pair of bipolar transistors and a plurality of MOSFETs; characterised in that: the basic cells (BC) are arranged in a predetermined pattern on the substrate (100), which predetermined pattern is such that said pair of bipolar transistors included in one of said basic cells are arranged near a certain latus of said one basic cell, and wherein said pair of bipolar transistors included in the other basic cell are arranged in mirror symmetry to said pair of bipolar transistors of said one basic cell with respect to said certain latus.
Claim 3
Dependent Claim
105 words
A semiconductor integrated circuit comprising: a semiconductor substrate (100) which has a principal surface; and a plurality of basic cells (BC) which are on the principal surface and each of which includes a pair of bipolar transistors and a plurality of MOSFETs; characterised in that: the basic cells (BC) are arranged in a predetermined pattern on the substrate (100), which predetermined pattern is such that the basic cells (BC) comprise a first type of cell containing CMOS logic gate circuits and a second type of cell containing Bi-CMOS logic gate circuits, and the numbers of first and second types of cells have a predetermined ratio.
Claim 4
Dependent Claim
105 words
A semiconductor integrated circuit comprising: a semiconductor substrate (100) which has a principal surface; and a plurality of basic cells (BC) which are on the principal surface and each of which includes a pair of bipolar transistors and a plurality of MOSFETs; characterised in that: the basic cells (BC) are arranged in a predetermined pattern on the substrate (100), which predetermined pattern is such that the basic cells (BC) comprise a first type of cell containing CMOS logic gate circuits and a second type of cell containing Bi-CMOS logic gate circuits, and the numbers of first and second types of cells have a predetermined ratio.
Claim 5
Dependent Claim
67 words
A semiconductor integrated circuit according to claim 1 or claim 2, wherein one basic cell includes a first Bi-CMOS circuit in which one of the bipolar transistors forms an output transistor with a first emitter size. and another basic cell includes a second Bi-CMOS circuit in which one of the bipolar transistors forms an output transistor with a second emitter size larger than the first emitter size.
Claim 6
Dependent Claim
43 words
A semiconductor integrated circuit according to any one of the preceding claims wherein at least some of the basic cells have an output transistor, and at least one of the bipolar transistors of the cells is connected in parallel to the output transistor.
Claim 7
Dependent Claim
65 words
A semidconductor integrated circuit according to any one of the preceding claims, having a first power supply terminal which is fed with a first power supply voltage; a second power supply terminal which is fed with a second power supply voltage lower than the first power supply voltage; an input terminal which receives an input signal; and an output terminal which delivers an output signal.
Claim 8
Dependent Claim
223 words
A semiconductor integrated circuit according to claim 5, wherein at least some of the basic cells (BC) have a first bipolar transistor which has an emitter-collector path coupled across said first power supply terminal and said output terminal; a second bipolar transistor which has an emitter- collector path coupled in parallel with the emitter-collector path of said first bipolar transistor, and a base coupled to a base of said first bipolar transistor; a third bipolar transistor which has an emitter-collector path coupled across said second power supply terminal and said output terminal; a fourth bipolar transistor which has an emitter-collector path coupled in parallel with the emitter collector path of said third bipolar transistor, and a base coupled to a base of said third bipolar transistor; and a CMOS circuit which is coupled across said first and second power supply terminals; said CMOS circuit including an input coupled to said input terminal, a first output coupled to the base of said first bipolar transistor, a second output coupled to the base of said third bipolar transistor, a P-MOSFET having a gate coupled to said input and a source-drain path coupled across said first power supply terminal and said first output, and an N-MOSFET having a gate coupled to said input and a source-drain path coupled across said output terminal and said second output.
Claim 9
Dependent Claim
257 words
A logic circuit comprising: a first power supply terminal which is fed with a first power supply voltage; a second power supply terminal which is fed with a second power supply voltage lower than the first power supply voltage; an input terminal which receives an input signal; an output terminal which delivers an output signal; a first bipolar transistor which has an emitter-collector path coupled across said first power supply terminal and said output terminal; a second bipolar transistor which has an emitter-collector path coupled in parallel with the emitter-collector path of said first bipolar transistor, and a base coupled to a base of said first bipolar transistor; a third bipolar transistor which has an emitter-collctor path coupled across said second power-supply terminal and said output terminal; a fourth bipolar transistor which has an emitter-collector path coupled in parallel with the emitte-collector path of said third bipolar transistor, and a base coupled to a base of said third bipolar transistor; and a CMOS circuit which is coupled across said first and second power supply terminals; said CMOS circuit including an input coupled to said input terminal, a first output coupled to the base of said first bipolar transistor, a second output coupled to the base of said third bipolar transistor, a P-MOSFET having a gate coupled to said input and a source-drain path coupled across said first power supply terminal and said first output, and an N-MOSFET having a gate coupled to said input and a source-drain path coupled across said ouput terminal and said second output.
Claim 10
Dependent Claim
257 words
A logic circuit comprising: a first power supply terminal which is fed with a first power supply voltage; a second power supply terminal which is fed with a second power supply voltage lower than the first power supply voltage; an input terminal which receives an input signal; an output terminal which delivers an output signal; a first bipolar transistor which has an emitter-collector path coupled across said first power supply terminal and said output terminal; a second bipolar transistor which has an emitter-collector path coupled in parallel with the emitter-collector path of said first bipolar transistor, and a base coupled to a base of said first bipolar transistor; a third bipolar transistor which has an emitter-collctor path coupled across said second power-supply terminal and said output terminal; a fourth bipolar transistor which has an emitter-collector path coupled in parallel with the emitte-collector path of said third bipolar transistor, and a base coupled to a base of said third bipolar transistor; and a CMOS circuit which is coupled across said first and second power supply terminals; said CMOS circuit including an input coupled to said input terminal, a first output coupled to the base of said first bipolar transistor, a second output coupled to the base of said third bipolar transistor, a P-MOSFET having a gate coupled to said input and a source-drain path coupled across said first power supply terminal and said first output, and an N-MOSFET having a gate coupled to said input and a source-drain path coupled across said ouput terminal and said second output.
Claim 11
Dependent Claim
36 words
A basic cell for use in a semiconductor integrated circuit according to any one of claims 1 to 6, comprising: at least four bipolar transistors; a plurality of P-channel MOSFETs; and a plurality of N-channel MOSFETs.
Claim 12
Dependent Claim
32 words
A basic cell for use in a gate array which includes bipolar transistors and MOSFETs, comprising: at least four bipolar transistors; a plurality of P-channel MOSFETs; and a plurality of N-channel MOSFETs.
Claim 13
Dependent Claim
32 words
A basic cell for use in a gate array which includes bipolar transistors and MOSFETs, comprising: at least four bipolar transistors; a plurality of P-channel MOSFETs; and a plurality of N-channel MOSFETs.
Claim 14
Independent Claim
228 words
A method of designing a semiconductor logic circuit, comprising the steps of: (1) finding a relationship between a propagation delay time t pd1 and an output load capcitance of a CMOS circuit; (2) finding a relationship between a propagation delay time t pd2 and an output load capacitance of a first Bi-CMOS circuit whose output bipolar transistor has a predetermined emitter area; (3) finding a relationship between a propagation delay time t pd3 and an output load capacitance of a second Bi-CMOS circuit whose output bipolar transistor has an emitter area larger than that of the output bipolar transistor of said first Bi-CMOS circuit; (4) finding a relationship between the output load capcitance and the propagation delay times t pd1 , t pd2 and t pd3 from the relationships found at said steps (1), (2) and (3); (5) finding an output load capacitance CL of the logic circuit to be designed; and (6) selecting a circuit form capable of charging and discharging the output load capacitance CL fastest, from among said CMOS circuit, said first Bi-CMOS circuit and said second Bi-CMOS circuit on the basis of the relationship between the output load capacitance and the propagation delay times t pd1 , t pd2 and t pd3 as found at said step (4) and the output load capacitance CL of said logic circuit as found at said step (5).
Claim 15
Independent Claim
228 words
A method of designing a semiconductor logic circuit, comprising the steps of: (1) finding a relationship between a propagation delay time t pd1 and an output load capcitance of a CMOS circuit; (2) finding a relationship between a propagation delay time t pd2 and an output load capacitance of a first Bi-CMOS circuit whose output bipolar transistor has a predetermined emitter area; (3) finding a relationship between a propagation delay time t pd3 and an output load capacitance of a second Bi-CMOS circuit whose output bipolar transistor has an emitter area larger than that of the output bipolar transistor of said first Bi-CMOS circuit; (4) finding a relationship between the output load capcitance and the propagation delay times t pd1 , t pd2 and t pd3 from the relationships found at said steps (1), (2) and (3); (5) finding an output load capacitance CL of the logic circuit to be designed; and (6) selecting a circuit form capable of charging and discharging the output load capacitance CL fastest, from among said CMOS circuit, said first Bi-CMOS circuit and said second Bi-CMOS circuit on the basis of the relationship between the output load capacitance and the propagation delay times t pd1 , t pd2 and t pd3 as found at said step (4) and the output load capacitance CL of said logic circuit as found at said step (5).
References Cited (Backward Citations)
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