EP0170268A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Complementary MOS integrated circuit having means for preventing latch-up phenomenon
Assignee: NEC Corp
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Filing: 1985-07-30
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Granted: —
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Expires: 2005-07-30
Abstract
Abstract The complementary MOS integrated circuit has a first channel MOS FET in a substrate of one conductivity type and a second channel MOS FET in a well region of the other conductivity type, and further comprises a first high impurity region of the one conductivity type formed in the substrate so as to surround the first channel MOS FET, a second high impurity region of the other conductivity type formed in the well region so as to surround the second channel MOS FET, a first insulator film covering the first and second high impurity regions and having a plurality of first holes, a first wiring layer formed on the first insulator film with connections with the first high impurity region through the first holes, so as to surround the first channel MOS FET, a second wiring layer formed on the first insulator film with connections with the second high impurity region through the second holes, so as to surround the second channel MOS FET, a second insulator film covering the first and second wiring layers and having a plurality of second holes, a third wiring layer formed on the second insulator film, connected with the first wiring layer through the second holes and supplied with a first power potential, and a fourth wiring layer formed on the second insulator film, connected with the second wiring layer through the second holes and supplied with a second power potential.
Inventors
- 👤 Masaki Ebina
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 14:38
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
229 words
An MOS integrated circuit comprising: a semiconductor substrate of one conductivity type; a well-region of the other conductivity type formed in the semiconductor substrate; a first MOS field effect transistor of one conductivity type formed in said well-region; a second MOS field effect transistors of the other conductivity type formed in said semiconductor substrate outside said well region; a high impurity region formed in said well region and having said other conductivity type, said high impurity region surrounding substantially said first MOS field effect transistor; a circuit means for wiring said first and second MOS field effect transistors to form a circuit; a first insulator film covering said high impurity region and having a plurality of first holes exposing a plurality of contact portions of said high impurity region; a first wiring layer covering said first insulator film and connected with said contact portions of said high impurity region through said first holes, said first wiring layer substantially surrounding said first MOS field effect transistor; a second insulator film covering said first wiring layer and having a plurality of second holes exposing a plurality of contact portions of said first wiring layer; a second wiring layer covering said second insulator film and connected with said contact portions of said first wiring layer through said second holes; and a means for supplying a constant potential to said second wiring layer.
Claim 2
Dependent Claim
229 words
An MOS integrated circuit comprising: a semiconductor substrate of one conductivity type; a well-region of the other conductivity type formed in the semiconductor substrate; a first MOS field effect transistor of one conductivity type formed in said well-region; a second MOS field effect transistors of the other conductivity type formed in said semiconductor substrate outside said well region; a high impurity region formed in said well region and having said other conductivity type, said high impurity region surrounding substantially said first MOS field effect transistor; a circuit means for wiring said first and second MOS field effect transistors to form a circuit; a first insulator film covering said high impurity region and having a plurality of first holes exposing a plurality of contact portions of said high impurity region; a first wiring layer covering said first insulator film and connected with said contact portions of said high impurity region through said first holes, said first wiring layer substantially surrounding said first MOS field effect transistor; a second insulator film covering said first wiring layer and having a plurality of second holes exposing a plurality of contact portions of said first wiring layer; a second wiring layer covering said second insulator film and connected with said contact portions of said first wiring layer through said second holes; and a means for supplying a constant potential to said second wiring layer.
Claim 3
Dependent Claim
22 words
An MOS integrated circuit as claimed in claim 1, wherein said second holes are disposed between said first holes in plan view.
Claim 4
Dependent Claim
145 words
An MOS integrated circuit as claimed in claim 1, further comprising: another high impurity region formed in the substrate outside said well-region, said other high impurity region substantially surrounding said second MOS field effect transistor; a third insulator film covering said other high impurity region and having a plurality of third holes exposing said other high impurity region; a third wiring layer covering said third insulator film and connected with said other high impurity region through said third holes, said third wiring layer substantially surrounding said second MOS field effect transistor; a fourth insulator film covering said third wiring layer and having a plurality of fourth holes exposing said third wiring layer; a fourth wiring layer covering said fourth insulator film and connected with said third wiring layer through said fourth holes and a means for supplying a power voltage to said fourth wiring layer.
Claim 5
Dependent Claim
32 words
An MOS integrated circuit as claimed in claim 3, wherein said second holes and said fourth holes are respectively disposed in plan view between said first holes and between said third holes.
Claim 6
Dependent Claim
29 words
An MOS integrated circuit as claimed in claim 4, wherein said first, second, third and fourth holes are respectively disposed with an interval between 2 µm and 5 µm.
Claim 7
Dependent Claim
101 words
A structure of interconnection between a region of a semiconductor substrate and a wiring layer, said structure comprising: a semiconductor substrate having a region; a first insulator film covering said region and having first holes exposing said region; a first wiring layer formed on said first insulator film and connected with said region through said first holes; a second insulator film covering said first wiring layer and having second holes each disposed between said first holes in plan view; and a second wiring layer formed on said second insulator film and connected with said first wiring layer through said second holes.
Claim 8
Dependent Claim
101 words
A structure of interconnection between a region of a semiconductor substrate and a wiring layer, said structure comprising: a semiconductor substrate having a region; a first insulator film covering said region and having first holes exposing said region; a first wiring layer formed on said first insulator film and connected with said region through said first holes; a second insulator film covering said first wiring layer and having second holes each disposed between said first holes in plan view; and a second wiring layer formed on said second insulator film and connected with said first wiring layer through said second holes.
References Cited (Backward Citations)
No citation records indexed.
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