Method of fabricating a miniaturized heterojunction bipolar transistor

Claim 1

A method of fabricating a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer, said method comprising the steps of: forming a first silicon layer of a first conductivity type on a substrate, said first silicon layer serving as a collector layer; etching a selected portion of the first silicon layer to form a groove which defines an area of said collector layer, and burying an insulating layer in said groove, said insulating layer having a top surface being substantially flush with that of said first silicon layer; forming a silicon-germanium alloy layer of a second conductivity type, serving as a base layer, on the first silicon layer and that part of the insulating layer surrounding the first silicon layer; forming a second silicon layer of the first conductivity type, serving as an emitter layer, on the silicon-germanium alloy layer; and selectively doping an impurity of the second conductivity type into said base layer, said emitter layer and said collector layer, thereby to provide a heavily-doped layer serving as an external base layer, said external base layer having opposing edge portions between which the emitter and base layers are located and a distance between which is smaller than a width of said collector layer.

Claim 2

A method of fabricating a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer, said method comprising the steps of: forming a first silicon layer of a first conductivity type on a substrate, said first silicon layer serving as a collector layer; etching a selected portion of the first silicon layer to form a groove which defines an area of said collector layer, and burying an insulating layer in said groove, said insulating layer having a top surface being substantially flush with that of said first silicon layer; forming a silicon-germanium alloy layer of a second conductivity type, serving as a base layer, on the first silicon layer and that part of the insulating layer surrounding the first silicon layer; forming a second silicon layer of the first conductivity type, serving as an emitter layer, on the silicon-germanium alloy layer; and selectively doping an impurity of the second conductivity type into said base layer, said emitter layer and said collector layer, thereby to provide a heavily-doped layer serving as an external base layer, said external base layer having opposing edge portions between which the emitter and base layers are located and a distance between which is smaller than a width of said collector layer.

Claim 6

A method of fabricating a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer, said method comprising the steps of: forming a first silicon layer of a first conductivity type on a substrate, said first silicon layer serving as a collector layer; etching an unnecessary portion of the first silicon layer to form a groove, and burying a first insulating layer in said groove; epitaxially growing a silicon-germanium alloy layer of a second conductivity type, serving as a base layer, on the first silicon layer and that part of the first insulating layer surrounding the first silicon layer; forming successively a second silicon layer of the first conductivity type, which will become an emitter layer, and a third silicon layer of the first conductivity type, which will become an emitter-contact layer, on the surface of the silicon-germanium alloy layer; patterning a second insulating layer on the third silicon layer so as to cover the emitter region, and, using the second insulating layer as a mask, etching and removing the third silicon layer; selectively forming a third insulating layer on a side wall of a laminated structure of the third silicon layer and the second insulating layer; and doping an impurity in the silicon-germanium alloy layer and the second silicon layer, with the second and third insulating layers used as a mask, thereby forming an external base layer of the second conductivity type.

Claim 7

A method of fabricating a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer, said method comprising the steps of: forming a first silicon layer of a first conductivity type on a substrate, said first silicon layer serving as a collector layer; etching an unnecessary portion of the first silicon layer to form a groove, and burying a first insulating layer in said groove; epitaxially growing a silicon-germanium alloy layer of a second conductivity type, serving as a base layer, on the first silicon layer and that part of the first insulating layer surrounding the first silicon layer; forming successively a second silicon layer of the first conductivity type, which will become an emitter layer, and a third silicon layer of the first conductivity type, which will become an emitter-contact layer, on the surface of the silicon-germanium alloy layer; patterning a second insulating layer on the third silicon layer so as to cover the emitter region, and, using the second insulating layer as a mask, etching and removing the third silicon layer; selectively forming a third insulating layer on a side wall of a laminated structure of the third silicon layer and the second insulating layer; and doping an impurity in the silicon-germanium alloy layer and the second silicon layer, with the second and third insulating layers used as a mask, thereby forming an external base layer of the second conductivity type.

Claim 11

A method of fabricating a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer, said method comprising the steps of: forming a first silicon layer of a first conductivity type on a substrate, said first silicon layer serving as a collector layer; etching an unnecessary portion of the first silicon layer to form a groove, and burying a first insulating layer in said groove; epitaxially growing a first silicon-germanium alloy of a second conductivity type, serving as a base layer, on the first silicon layer and that part of the insulating layer surrounding the first silicon layer; forming successively a second silicon layer of the first conductivity type, which will become an emitter layer, and a third silicon layer of the first conductivity type, which will become an emitter-contact layer, on the surface of the first silicon-germanium alloy layer; patterning a second insulating layer on the third silicon layer so as to cover the emitter region, and, using the second insulating layer as a mask, etching and removing the third silicon layer; selectively forming a third insulating layer on a side wall of a laminated structure of the third silicon layer and the second insulating layer; etching and removing the second silicon layer, with the second and third insulating layers used as a mask, and subsequently etching the first silicon-germanium alloy layer to a predetermined thickness; epitaxially growing a second silicon-germanium alloy layer serving as an external base layer on the remaining first silicon-germanium alloy layer, said second silicon-germanium alloy layer having a narrower band gap than the first silicon-germanium alloy layer and a greater thickness than the first silicon-germanium alloy layer; and doping an impurity in the second silicon-germanium alloy layer, thereby forming an external base layer of the second conductivity type.

Claim 12

A method of fabricating a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer, said method comprising the steps of: forming a first silicon layer of a first conductivity type on a substrate, said first silicon layer serving as a collector layer; etching an unnecessary portion of the first silicon layer to form a groove, and burying a first insulating layer in said groove; epitaxially growing a first silicon-germanium alloy of a second conductivity type, serving as a base layer, on the first silicon layer and that part of the insulating layer surrounding the first silicon layer; forming successively a second silicon layer of the first conductivity type, which will become an emitter layer, and a third silicon layer of the first conductivity type, which will become an emitter-contact layer, on the surface of the first silicon-germanium alloy layer; patterning a second insulating layer on the third silicon layer so as to cover the emitter region, and, using the second insulating layer as a mask, etching and removing the third silicon layer; selectively forming a third insulating layer on a side wall of a laminated structure of the third silicon layer and the second insulating layer; etching and removing the second silicon layer, with the second and third insulating layers used as a mask, and subsequently etching the first silicon-germanium alloy layer to a predetermined thickness; epitaxially growing a second silicon-germanium alloy layer serving as an external base layer on the remaining first silicon-germanium alloy layer, said second silicon-germanium alloy layer having a narrower band gap than the first silicon-germanium alloy layer and a greater thickness than the first silicon-germanium alloy layer; and doping an impurity in the second silicon-germanium alloy layer, thereby forming an external base layer of the second conductivity type.

Claim 16

A method of fabricating a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer, said method comprising the steps of: forming a first silicon layer of a first conductivity type on a substrate, said first silicon layer serving as a collector layer; etching an unnecessary portion of the first silicon layer to form a groove, and burying a first insulating layer in said groove; epitaxially growing a first silicon-germanium alloy layer of a second conductivity type, serving as a first internal base layer, on the first silicon layer and that part of the insulating layer surrounding the first silicon layer, and patterning the first silicon-germanium alloy layer so as to leave the first silicon-germanium alloy layer at a central part of an internal base region; epitaxially growing a second silicon-germanium alloy layer serving as a second internal base layer continuous with the periphery of said patterned first silicon-germanium alloy layer, said second silicon-germanium alloy layer having a narrower band gap than the first silicon-germanium alloy layer; forming successively a second silicon layer of the first conductivity type, which will become an emitter layer, and a third silicon layer of the first conductivity type, which will become an emitter-contact layer, on the surfaces of the first and second silicon-germanium alloy layers; patterning a second insulating layer on the third silicon layer so as to cover the emitter region, and, using the second insulating layer as a mask, etching and removing the third silicon layer; selectively forming a third insulating layer on a side wall of a laminated structure of the third silicon layer and the second insulating layer; and doping an impurity in the second silicon-germanium alloy layer and the second silicon layer, with the second and third insulating layers used as a mask, thereby forming an external base layer of the second conductivity type.

Claim 17

A method of fabricating a miniaturized heterojunction bipolar transistor wherein at least one of an emitter layer and a collector layer is formed of a semiconductor material having a wider band gap than a material of a base layer, said method comprising the steps of: forming a first silicon layer of a first conductivity type on a substrate, said first silicon layer serving as a collector layer; etching an unnecessary portion of the first silicon layer to form a groove, and burying a first insulating layer in said groove; epitaxially growing a first silicon-germanium alloy layer of a second conductivity type, serving as a first internal base layer, on the first silicon layer and that part of the insulating layer surrounding the first silicon layer, and patterning the first silicon-germanium alloy layer so as to leave the first silicon-germanium alloy layer at a central part of an internal base region; epitaxially growing a second silicon-germanium alloy layer serving as a second internal base layer continuous with the periphery of said patterned first silicon-germanium alloy layer, said second silicon-germanium alloy layer having a narrower band gap than the first silicon-germanium alloy layer; forming successively a second silicon layer of the first conductivity type, which will become an emitter layer, and a third silicon layer of the first conductivity type, which will become an emitter-contact layer, on the surfaces of the first and second silicon-germanium alloy layers; patterning a second insulating layer on the third silicon layer so as to cover the emitter region, and, using the second insulating layer as a mask, etching and removing the third silicon layer; selectively forming a third insulating layer on a side wall of a laminated structure of the third silicon layer and the second insulating layer; and doping an impurity in the second silicon-germanium alloy layer and the second silicon layer, with the second and third insulating layers used as a mask, thereby forming an external base layer of the second conductivity type.