US4997776A
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Complementary bipolar transistor structure and method for manufacture
Assignee: International Business Machines Corp
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Filing: 1990-06-20
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Granted: 1991-03-05
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Expires: 2010-06-20
Abstract
Abstract A complementary bipolar transistor structure having one symmetrical intrinsic region for both the NPN and PNP transistors and a method for fabricating the structure. The transistor structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. In the method, the sub-emitter and the sub-collector regions are formed by depositing a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, and forming the sub-collector by etchig a shallow trench in the first layer and depositing semiconductor material of a second conductivity tyep by LTE and planarizing. The intrinsic regions for both of the transistors are formed by depositing a second layer of semiconductor material of the second conductivity type on the surface of the first layer and a third layer of semiconductor material of the first conductivity type on the surface of the second layer by either LTE or MBE. In one embodiment, the second and third layers are provided with a uniform vertical doping profile for one thickness of the layer and a graded doping profile for the remaining thickness in which the minimum doping level for both graded portions is at the junction between the second and third layers. The second layers forms the base and the third layer forms the collector for one transistor while at the same time the second layer forms a collector and the third layer forms the base for the other transistor. The performance of the intrinsic base and collector regions can be further improved by forming the second and third layers with a compound semiconductor material, such as, the compound of Si-Ge to create a heterojunction transistor. Device and intrinsic region isolation is effected by a combination of deep trench and shallow trench processes and reach-through regions for the sub-emitter and sub-collector are formed. A layer of polysilicon is deposited and selectively etched to form an extrinsic collector region for one transistor and extrinsic base regions for the other transistor. A further loayer of single crystal silicon is deposited to form the extrinsic base region for one transistor and the emitter for the other transistor.
Inventors
- 👤 David L. Harame
- 👤 Gary L. Patton
- 👤 Maria C. Stork
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:59
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/67; H10D84/673; H10D84/01; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/06
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
328 words
A method of fabricating a transistor structure including a complementary pair of vertical bipolar transistors on a common semiconductor substrate, the method comprising: (a) forming a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, said first epitaxial layer forming a sub-emitter region for one of said complementary transistors; (b) forming a sub-collector region of a second conductivity type for the other of said complementary transistors in the first layer; (c) forming a second epitaxial layer of semiconductor material of said second conductivity type on the surface of said first layer; (d) forming a third epitaxial layer of semiconductor material of said first conductivity type on the surface of said second layer; (e) forming deep recessed isolation regions extending from the surface of said third layer into said substrate, said deep isolation regions surrounding each of said transistors; (f) forming shallow recessed isolation regions in said second and third layers for defining intrinsic base and collector regions of said one transistor in said second and third layers respectively and for defining intrinsic collector and base regions of said other transistor in said second and third layers respectively; (g) forming simultaneously a pair of extrinsic base regions of said first conductivity type on the surface of said third layer for said other transistor, and an emitter reach-through region of said first conductivity type in said second and third layers and an extrinsic collector region of said first conductivity type on the surface of said third layer for said one transistor; and (h) forming simultaneously an extrinsic base region of said second conductivity type for said one transistor overlying said collector region of said first conductivity type, and a sub-collector reach-through region of said second conductivity type formed in said second and third layers and an emitter region of said second conductivity type for said other transistor overlying said base region of said first conductivity type.
Claim 2
Independent Claim
328 words
A method of fabricating a transistor structure including a complementary pair of vertical bipolar transistors on a common semiconductor substrate, the method comprising: (a) forming a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, said first epitaxial layer forming a sub-emitter region for one of said complementary transistors; (b) forming a sub-collector region of a second conductivity type for the other of said complementary transistors in the first layer; (c) forming a second epitaxial layer of semiconductor material of said second conductivity type on the surface of said first layer; (d) forming a third epitaxial layer of semiconductor material of said first conductivity type on the surface of said second layer; (e) forming deep recessed isolation regions extending from the surface of said third layer into said substrate, said deep isolation regions surrounding each of said transistors; (f) forming shallow recessed isolation regions in said second and third layers for defining intrinsic base and collector regions of said one transistor in said second and third layers respectively and for defining intrinsic collector and base regions of said other transistor in said second and third layers respectively; (g) forming simultaneously a pair of extrinsic base regions of said first conductivity type on the surface of said third layer for said other transistor, and an emitter reach-through region of said first conductivity type in said second and third layers and an extrinsic collector region of said first conductivity type on the surface of said third layer for said one transistor; and (h) forming simultaneously an extrinsic base region of said second conductivity type for said one transistor overlying said collector region of said first conductivity type, and a sub-collector reach-through region of said second conductivity type formed in said second and third layers and an emitter region of said second conductivity type for said other transistor overlying said base region of said first conductivity type.
Claim 3
Dependent Claim
33 words
The method of claim 1 wherein said one transistor and said other transistor are NPN and PNP transistors, respectively, and wherein said first and second conductivity types are N-type and P-type conductivity, respectively.
Claim 4
Dependent Claim
145 words
The method of claim 1 wherein steps (a) and (b) comprise: depositing said first epitaxial layer by molecular beam epitaxy (MBE), said first layer being heavily doped, depositing a layer of insulating material on said first layer, forming a masking layer on said insulating layer having a window and etching a portion of said first layer through said window leaving a mesa-like region of said first layer; depositing a blanket layer of semiconductor material of said second conductivity type by low temperature epitaxy (LTE) on the substrate assembly; forming a masking layer on said blanket layer over said window and over a portion of said mesa-like region of said first layer, etching the non-masked region of said blanket layer to said insulating layer and planarizing the substrate assembly to provide a sub-collector region having a planar surface with said mesa-like region of said first layer.
Claim 5
Dependent Claim
17 words
The method of claim 3 wherein the LTE is performed by ultra high vacuum chemical vapor deposition.
Claim 6
Dependent Claim
15 words
The method of claim 3 wherein the planarizing is performed by chemical and mechanical polishing.
Claim 7
Dependent Claim
32 words
The method of claim 1 wherein step (c) includes depositing said second layer with a uniform vertical doping profile for a first thickness and a graded doping profile for the remaining thickness.
Claim 8
Dependent Claim
33 words
The method of claim 6 wherein step (d) includes depositing said third layer with a graded vertical doping profile for a first thickness and a uniform vertical doping profile for the remaining thickness.
Claim 9
Dependent Claim
41 words
The method of claim 7 wherein said second and third layers are deposited with a uniform doping profile of about 2×10 8 cm -3 and a graded doping profile from about 1×10 17 cm -3 to 2×10 18 cm -3 .
Claim 10
Dependent Claim
31 words
The method of claim 8 wherein the doping level of both said second and third layers is about 1×10 17 cm -3 at the junction between said second and third layers.
Claim 11
Dependent Claim
23 words
The method of claim 9 wherein said first thickness and said remaining thickness of both said second and third layers are approximately equal.
Claim 12
Dependent Claim
21 words
The method of claim 10 wherein said first thickness and said remaining thickness are each in the range of 25-50 nm.
Claim 13
Dependent Claim
15 words
The method of claim 11 wherein said second and third layers are deposited by MBE.
Claim 14
Dependent Claim
15 words
The method of claim 11 wherein said second and third layers are deposited by LTE.
Claim 15
Dependent Claim
19 words
The method of claim 1 wherein step (c) includes depositing a compound semiconductor material to form said second layer.
Claim 16
Dependent Claim
19 words
The method of claim 1 wherein step (d) include depositing a compound semiconductor material to form said third layer.
Claim 17
Dependent Claim
19 words
The method of claim 15 wherein said second and third layers comprise a compound semiconductor of silicon and germanium.
Claim 18
Dependent Claim
30 words
The method of claim 16 wherein said second and third layers are deposited with a graded Ge content having a peak at the junction between said second and third layers.
Claim 19
Dependent Claim
43 words
The method of claim 1 wherein step (e) includes forming a masking layer having windows on said third layer, etching the surface of said substrate and said first, second and third layers through said window and forming insulating material in said etched areas.
Claim 20
Dependent Claim
17 words
The method of claim 18 wherein the insulating material is formed by thermally oxidizing the etched areas.
Claim 21
Dependent Claim
25 words
The method of claim 18 wherein the insulating material is formed by depositing one of silicon dioxide and silicon nitride by chemical vapor deposition (CVD).
Claim 22
Dependent Claim
43 words
The method of claim 1 wherein step (f) includes forming a masking layer having windows on said third layer, etching the surface of said first layer and said second and third layers through said windows and forming insulating material in said etched areas.
Claim 23
Dependent Claim
17 words
The method of claim 21 wherein the insulating material is formed by thermally oxidizing the etched areas.
Claim 24
Dependent Claim
22 words
The method of claim 21 wherein the insulating material is formed by depositing one of silicon dioxide and silicon nitride by CVD.
Claim 25
Dependent Claim
35 words
The method of claim 1 wherein step (g) includes forming a masking layer having a window on said third layer for said emitter reach-through region and etching said second and third layers through said window.
Claim 26
Dependent Claim
47 words
The method of claim 24 wherein step (g) includes depositing a fourth layer of semiconductor material of said first conductivity type on the top surface of the substrate assembly, forming a masking layer having windows on said fourth layer and etching said fourth layer through said windows.
Claim 27
Dependent Claim
26 words
The method of claim 25 wherein step (g) includes forming oxide sidewalls on exposed surfaces of the fourth layer forming the extrinsic base and collector regions.
Claim 28
Dependent Claim
22 words
The method of claim 25 wherein said fourth layer is deposited by low pressure chemical vapor deposition and has a polycrystalline structure.
Claim 29
Dependent Claim
35 words
The method of claim 1 wherein step (h) includes forming a masking layer having a window on said third layer for said collector reach-through region and etching said second and third layers through said window.
Claim 30
Dependent Claim
39 words
The method of claim 28 wherein step (h) includes forming a masking layer having windows surrounding said extrinsic collector region of said one transistor and etching the third layer and the surface of the second layer through said window.
Claim 31
Dependent Claim
48 words
The method of claim 29 wherein step (h) includes depositing a fifth epitaxial layer of semiconductor material of said second conductivity type on the top surface of the substrate assembly, forming a masking layer having windows on said fifth layer and etching said fifth layer through said windows.
Claim 32
Dependent Claim
17 words
The method of claim 30 wherein said fifth layer is deposited by one of LTE and MBE.
Claim 33
Dependent Claim
17 words
The method of claim 31 wherein said LTE is deposited in an ultra high vacuum CVD system.
Claim 34
Dependent Claim
19 words
The method of claim 32 wherein the emitter of said other transistor is deposited with a steep doping profile.
Claim 35
Dependent Claim
34 words
The method of claim 1 further including forming simultaneously a base contact of said second conductivity type for said one transistor and a collector contact of said second conductivity type for said other transistor.
Claim 36
Dependent Claim
34 words
The method of claim 34 further including forming simultaneously an emitter contact of said first conductivity type for said one transistor and a base contact of said first conductivity type for said other transistor.
Claim 37
Independent Claim
349 words
A method of fabricating a transistor structure including a complementary pair of vertical bipolar transistors on a common semiconductor substrate, the method comprising: (a) forming a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, said first epitaxial layer forming a sub-emitter region for one of said complementary transistors; (b) forming a sub-collector region of a second conductivity type for the other of said complementary transistors in the first layer; (c) forming a second epitaxial layer of semiconductor material of said second conductivity type on the surface of said first layer; (d) forming a third epitaxial layer of semiconductor material of said first conductivity type on the surface of said second layer; (e) forming said second and third layers with a doping profile symmetrical about the junction between said second and third layers; (f) forming deep recessed isolation regions extending from the surface of said third layer into said substrate, said deep isolation regions surrounding each of said transistors; (g) forming shallow recessed isolation regions in said second and third layers for defining intrinsic base and collector regions of said one transistor in said second and third layers respectively and for defining intrinsic collector and base regions of said other transistor in said second and third layers respectively; (h) forming simultaneously a pair of extrinsic base regions of said first conductivity type on the surface of said third layer for said other transistor, and an emitter reach-through region of said first conductivity type in said second and third layers and an extrinsic collector region of said first conductivity type on the surface of said third layer for said one transistor; and (i) forming simultaneously an extrinsic base region of said second conductivity type for said one transistor overlying said collector region of said first conductivity type, and a sub-collector reach-through region of said second conductivity type formed in said second and third layers and an emitter region of said second conductivity type for said other transistor overlying said base region of said first conductivity type.
Claim 38
Independent Claim
349 words
A method of fabricating a transistor structure including a complementary pair of vertical bipolar transistors on a common semiconductor substrate, the method comprising: (a) forming a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, said first epitaxial layer forming a sub-emitter region for one of said complementary transistors; (b) forming a sub-collector region of a second conductivity type for the other of said complementary transistors in the first layer; (c) forming a second epitaxial layer of semiconductor material of said second conductivity type on the surface of said first layer; (d) forming a third epitaxial layer of semiconductor material of said first conductivity type on the surface of said second layer; (e) forming said second and third layers with a doping profile symmetrical about the junction between said second and third layers; (f) forming deep recessed isolation regions extending from the surface of said third layer into said substrate, said deep isolation regions surrounding each of said transistors; (g) forming shallow recessed isolation regions in said second and third layers for defining intrinsic base and collector regions of said one transistor in said second and third layers respectively and for defining intrinsic collector and base regions of said other transistor in said second and third layers respectively; (h) forming simultaneously a pair of extrinsic base regions of said first conductivity type on the surface of said third layer for said other transistor, and an emitter reach-through region of said first conductivity type in said second and third layers and an extrinsic collector region of said first conductivity type on the surface of said third layer for said one transistor; and (i) forming simultaneously an extrinsic base region of said second conductivity type for said one transistor overlying said collector region of said first conductivity type, and a sub-collector reach-through region of said second conductivity type formed in said second and third layers and an emitter region of said second conductivity type for said other transistor overlying said base region of said first conductivity type.
Claim 39
Dependent Claim
79 words
The method of claim 36 wherein step (e) includes providing said second layer with a uniform vertical doping profile for a first thickness and a graded doping profile for the remaining thickness, and providing said third layer with a graded vertical doping profile for a first thickness and a uniform vertical doping profile for the remaining thickness, wherein the minimum doping levels for both said second and third layers is at the junction between said second and third layers.
Claim 40
Dependent Claim
23 words
The method of claim 37 wherein steps (c) and (d) include depositing a compound semiconductor material to form said second and third layers.
Claim 41
Dependent Claim
19 words
The method of claim 38 wherein said second and third layers comprise a compound semiconductor of silicon and germanium.
Claim 42
Dependent Claim
30 words
The method of claim 39 wherein said second and third layers are deposited with a graded Ge content having a peak at the junction between said second and third layers.
References Cited (Backward Citations)
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