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US5247482A
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US
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Semiconductor memory device with high speed write operation
Assignee: Samsung Electronics Co Ltd
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Filing: 1991-06-28
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Granted: 1993-09-21
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Expires: 2011-06-28
Abstract
Abstract A dynamic RAM for performing high speed write operation after performing read operation. The inventive device receives write data after pre-charging and equalizing a pair of bit lines, by using a equalization signal activated for a predetermined time, at a time point at which a write enabling signal begins to be activated. Provided between the bit lines is an equalization circuit having an NMOS transistor of which gate is connected to the equalization signal depending on the write enabling signal.
Inventors
- 👤 Myoung-Ho Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:55
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C7/00; G11C7/12; G11C11/4076; G11C11/4094; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
172 words
A semiconductor memory device performing read and write functions in response to an external control signal, comprising: a pair of bit lines connected between a memory cell and a pair of input/output lines, for transmitting data therethrough during the reading and writing functions; write equalization means controllable in response to a write equalization signal depending on a write enabling signal, said write equalization means connected between said bit lines receiving an equalization voltage at a given level; equalization selecting means for transferring said write equalization signal to said write equalization means, said equalization selecting means being controlled in response to a column selection signal; column gate means connected between said input/output lines and said bit lines, said column gate means being controlled in response to said column selection signal; and means receiving a column address signal and said write enabling signal, for generating said write equalization signal, whereby said write equalization signal is activated for a predetermined time, at a time point at which said write enabling signal begins to be activated.
Claim 2
Dependent Claim
172 words
A semiconductor memory device performing read and write functions in response to an external control signal, comprising: a pair of bit lines connected between a memory cell and a pair of input/output lines, for transmitting data therethrough during the reading and writing functions; write equalization means controllable in response to a write equalization signal depending on a write enabling signal, said write equalization means connected between said bit lines receiving an equalization voltage at a given level; equalization selecting means for transferring said write equalization signal to said write equalization means, said equalization selecting means being controlled in response to a column selection signal; column gate means connected between said input/output lines and said bit lines, said column gate means being controlled in response to said column selection signal; and means receiving a column address signal and said write enabling signal, for generating said write equalization signal, whereby said write equalization signal is activated for a predetermined time, at a time point at which said write enabling signal begins to be activated.
Claim 3
Dependent Claim
63 words
A semiconductor memory device as claimed in claim 1, wherein said equalization selecting means comprises an insulating gate field effect transistor, a first terminal of channel of said transistor being connected to said write equalization signal, a second terminal of the channel of said transistor to said write equalization means, and the gate of said transistor being connected to said column selection signal.
Claim 4
Dependent Claim
86 words
A semiconductor memory device as claimed in claim 1 or 2, wherein said write equalization means comprises first, second and third metal-oxide-semiconductor (MOS) transistors, channels of said first and second MOS transistors being connected in series between said bit lines, said equalization voltage being applied a node formed at a connection of the channels of said first and second MOS transistors, gates of said first to third MOS transistors being commonly connected to said second terminal of the channel of said insulating gate field effect transistor.
Claim 5
Dependent Claim
49 words
A semiconductor memory device as claimed in claim 1, wherein said generating means comprises at least a logic gate, said logic gate having a first input terminal for receiving input signal without delay and a second input terminal for receiving said input signal with delay for a predetermined time.
Claim 6
Dependent Claim
105 words
A semiconductor memory device for transmitting external input data through a pair of bit lines to a selected memory cell, comprising: a first and second NMOS transistors having channels connected in series between said bit lines and gates connected to each other, an equalization voltage of a given level being applied to a connection of said channels thereof; a node commonly connected between said gates of said first and second NMOS transistors; and a third NMOS transistor having a first channel terminal connected to a write equalization signal, a second channel terminal connected to said node, and a gate connected to a column selection signal.
Claim 7
Dependent Claim
105 words
A semiconductor memory device for transmitting external input data through a pair of bit lines to a selected memory cell, comprising: a first and second NMOS transistors having channels connected in series between said bit lines and gates connected to each other, an equalization voltage of a given level being applied to a connection of said channels thereof; a node commonly connected between said gates of said first and second NMOS transistors; and a third NMOS transistor having a first channel terminal connected to a write equalization signal, a second channel terminal connected to said node, and a gate connected to a column selection signal.
Claim 8
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 5, further comprising an NMOS transistor having a channel connected between said bit lines and a gate connected to said node.
Claim 9
Dependent Claim
26 words
A semiconductor memory device as claimed in claim 5, wherein said column selection signal controls column gate means connected between said bit lines and input/output lines.
Claim 10
Dependent Claim
34 words
A semiconductor memory device as claimed in claim 5, wherein said write equalization signal is activated for a predetermined time, at a time point at which said write enabling signal begins to be activated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-20 | 1997-03-22 | 1997-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-20 | 2001-03-22 | 2001-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-20 | 2005-03-22 | 2005-09-21 | $7700.00 | Window Closed / Lapsed |