Semiconductor memory circuit with control of bit line voltage balancing

Claim 1

A semiconductor memory circuit comprising: a plurality of bit lines extending in a first direction; a plurality of word lines extending in a second direction perpendicular to said first direction, said plurality of bit lines being arranged in pairs with each pair of bit lines forming a memory column of a first bit line and a second bit line, said plurality of bit line pairs forming a plurality of memory columns; a plurality of memory cells connected to either a first bit line or a second bit line of said memory columns, each of said plurality of word lines being connected to a first bit line memory cell or a second bit line memory cell in each of said plurality of memory columns; a plurality of dummy cells each connected to a first or second bit line of said memory columns; a first dummy word line connected to each first bit line dummy cell; a second dummy word line connected to each second bit line dummy cell; sense amplifier means, connected between each first bit line and second bit line, for sensing a voltage difference therebetween; FET means, connected between each first bit line and second bit line, for balancing voltages appearing thereon; selection means for selecting either said first or said second dummy word line for control of a specified dummy cell in each memory column; and balancing control means, operatively interconnected with said dummy word lines and said FET means, for detecting the termination of dummy word line selection by said selection means and activating said FET means in response thereto.