CMOS precharge and equalization circuit

Claim 2

A CMOS precharge and equalization circuit for use with memory cells coupled between paired bit lines in a static random access memory array comprising: a first precharge N-channel MOS transistor having its drain connected to a supply potential and its source connected to a bit line; a second precharge N-channel MOS transistor having its drain connected to the supply potential and its source connected to a second bit line; said first and second precharge transistors have their gates connected together and to a first input node for receiving a true precharge signal; a first equalization P-channel MOS transistor having its source connected to the first bit line and its drain connected to a common node which is coupled to current-sinking means disposed external to the memory array for sinking current; a second equalization P-channel MOS transistor having its source connected to the second bit line and its drain connected to the common node; and said first and second equalization transistors having their gates connected together and to a second input node for receiving a complementary equalization signal.

Claim 3

The CMOS precharge and equalization circuit as claimed in claim 1, wherein the sources of said N-channel transistors are precharged to a specified voltage level approximately equal to one threshold drop below the supply potential.

Claim 4

A CMOS precharge and equalization circuit for use with memory cells coupled between paired bit lines in a static random access memory array comprising: a first precharge P-channel MOS transistor having its source connected to a supply potential and its drain connected to a bit line; a second precharge P-channel MOS transistor having its source connected to the supply potential and its drain connected to a second bit line; said first and second precharge transistors have their gates connected together and to a first input node for receiving a complementary precharge signal; a first equalization N-channel MOS transistor having its source connected to the first bit line and its drain connected to a common node which is coupled to current-sourcing means disposed external to the memory array for sourcing current; a second equalization N-channel MOS transistor having its source connected to the second bit line and its drain connected to the common node; and said first and second equalization transistors having their gates connected together and to a second input node for receiving a true equalization signal.

Claim 5

A CMOS precharge and equalization circuit for use with memory cells coupled between paired bit lines in a static random access memory array comprising: a first precharge P-channel MOS transistor having its source connected to a supply potential and its drain connected to a bit line; a second precharge P-channel MOS transistor having its source connected to the supply potential and its drain connected to a second bit line; said first and second precharge transistors have their gates connected together and to a first input node for receiving a complementary precharge signal; a first equalization N-channel MOS transistor having its source connected to the first bit line and its drain connected to a common node which is coupled to current-sourcing means disposed external to the memory array for sourcing current; a second equalization N-channel MOS transistor having its source connected to the second bit line and its drain connected to the common node; and said first and second equalization transistors having their gates connected together and to a second input node for receiving a true equalization signal.

Claim 6

The CMOS precharge and equalization circuit as claimed in claim 3 wherein the drains of said P-channel transistors are precharged to a specified voltage level approximately equal to one threshold drop above the supply potential.