Dynamic RAM with active pull-up circuit

Claim 1

A semiconductor memory device comprising a plurality of pairs of bit lines connected with a plurality of memory cells, further comprising: a sense amplifier provided for each of said pairs of bit lines to bring potential of a bit line of a low level in each of said pairs of bit lines to a ground level after selection of said memory cells, and an active pull-up circuit for each of said pairs of bit lines to pull up potential of a bit line of a high level in each of said pairs of bit lines to a power supply potential after operation of said sense amplifier, each of said pairs of bit lines being precharged with a potential lower than said power supply potential before said selection of said memory cells, said active pull-up circuit comprising: a first transistor provided between a power supply and the corresponding one of said bit lines, a capacitor having an electrode connected to said first transistor, a second transistor provided between said corresponding one of said bit lines and said electrode of said capacitor, signal voltage applying means for applying, to another electrode of said capacitor, signal voltage for raising a gate potential of said first transistor through said capacitor, and gate potential control means for controlling a gate potential of said second transistor, said gate potential control means being adapted to control the gate potential so as not to turn on said second transistor during a period from the start of operation of said sense amplifier to the end of operation of said active pull-up circuit.