US4813022A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static memory with pull-up circuit for pulling-up a potential on a bit line
Assignee: Toshiba Corp
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Filing: 1987-12-22
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Granted: 1989-03-14
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Expires: 2007-12-22
Abstract
Abstract The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.
Inventors
- 👤 Masataka Matsui
- 👤 Tetsuya Iizuka
- 👤 Jun-ichi Tsujimoto
- 👤 Takayuki Ohtani
- 👤 Mitsuo Isobe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:06
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
111 words
A static memory comprising: a static memory cell made up of a flip-flop which comprises MOS N channel transistors, and a pair of transistors as transfer gates; pull-up means connected to a terminal for receiving a power source voltage and to a pair of bit lines, said pull-up means being made up of N channel MOS transistors for bit line pull-up; and precharge/equalize means made up of N channel transistors, for precharging and equalizing said pair of bit lines, the threshold voltage of said N channel transistors of said precharge/equalize means being set at a value smaller than the threshold voltage of said N channel MOS transistors of said pull-up means.
Claim 2
Dependent Claim
111 words
A static memory comprising: a static memory cell made up of a flip-flop which comprises MOS N channel transistors, and a pair of transistors as transfer gates; pull-up means connected to a terminal for receiving a power source voltage and to a pair of bit lines, said pull-up means being made up of N channel MOS transistors for bit line pull-up; and precharge/equalize means made up of N channel transistors, for precharging and equalizing said pair of bit lines, the threshold voltage of said N channel transistors of said precharge/equalize means being set at a value smaller than the threshold voltage of said N channel MOS transistors of said pull-up means.
Claim 3
Dependent Claim
33 words
The static memory according to claim 1, wherein said precharge/equalize means is a circuit which is connected to said pair of bit lines and to said terminal for receiving a power source voltage.
Claim 4
Dependent Claim
54 words
The static memory according to claim 1, further comprising: a pair of data lines connected to said pair of bit lines via a pair of transfer gates; and wherein said precharge/equalize means is a circuit which is connected to said pair of data lines and to said terminal for receiving a power source voltage.
Claim 5
Dependent Claim
71 words
The static memory according to claim 1 further comprising: a pair of data lines connected to said pair of bit lines via a pair of transfer gates; and wherein said precharge/equalize means includes a circuit connected to said pair of bit lines to said terminal for receiving a power source voltage, and a circuit connected to said pair of data lines and to said terminal for receiving a power source voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |