US4459497A
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Sense amplifier using different threshold MOS devices
Assignee: Motorola Solutions Inc
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Filing: 1982-01-25
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Granted: 1984-07-10
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Expires: 2002-01-25
Abstract
Abstract A sense amplifier quickly charges a column line to a first predetermined voltage level with first, second and third transistors and then charges the column to a second predetermined voltage by using only the second and third transistors. The second and third transistors continue charging to the second predetermined voltage by virtue of having a lower threshold voltage than the first transistor. If a selected memory cell in the column is in a conducting state, the column charges to only the first predetermined voltage for detection as a logic "0". If the selected memory cell in the column is in a non-conducting state, the column continues charging to the second predetermined voltage for detection as a logic "1".
Inventors
- 👤 Clinton C. K. Kuo
- 👤 Horst Leuschner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:52
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
140 words
A sense amplifier comprising: inverter means for providing a bias signal which is inversely proportional to a signal present at a charge node; a first transistor having a control electrode coupled to the bias signal, a first current electrode coupled to a power supply terminal, and a second current electrode coupled to the charge node; a second transistor having a control electrode coupled to the bias signal, a first current electrode coupled to the power supply terminal, and a second current electrode coupled to the charge node; a third transistor having a control electrode coupled to the bias signal, a first current electrode coupled to the charge node, and a second current electrode coupled to an output terminal and; load means coupled between the power supply terminal and the output terminal for dropping voltage in proportion to current passing therethrough.
Claim 2
Dependent Claim
140 words
A sense amplifier comprising: inverter means for providing a bias signal which is inversely proportional to a signal present at a charge node; a first transistor having a control electrode coupled to the bias signal, a first current electrode coupled to a power supply terminal, and a second current electrode coupled to the charge node; a second transistor having a control electrode coupled to the bias signal, a first current electrode coupled to the power supply terminal, and a second current electrode coupled to the charge node; a third transistor having a control electrode coupled to the bias signal, a first current electrode coupled to the charge node, and a second current electrode coupled to an output terminal and; load means coupled between the power supply terminal and the output terminal for dropping voltage in proportion to current passing therethrough.
Claim 3
Dependent Claim
40 words
The sense amplifier of claim 1 wherein the first transistor has a first characteristic theshold voltage and the second and third transistors each have a second characteristic threshold voltage, said first threshold voltage being larger than the second threshold voltage.
Claim 4
Dependent Claim
132 words
A circuit comprising: inverter means for providing a bias signal which is inversely proportional to a signal present at a charge node; a first transistor having a control electrode coupled to the bias signal, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the charge node, and having a characteristic threshold voltage; a second transistor having a control electrode coupled to the bias signal, a first current electrode coupled to the first power supply terminal, and a second current electrode coupled to the charge node, and having a characteristic threshold voltage which is different than the characteristic threshold voltage of the first transistor; and an output circuit having an input coupled to the charge node, and an output for providing an output signal.
Claim 5
Dependent Claim
132 words
A circuit comprising: inverter means for providing a bias signal which is inversely proportional to a signal present at a charge node; a first transistor having a control electrode coupled to the bias signal, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the charge node, and having a characteristic threshold voltage; a second transistor having a control electrode coupled to the bias signal, a first current electrode coupled to the first power supply terminal, and a second current electrode coupled to the charge node, and having a characteristic threshold voltage which is different than the characteristic threshold voltage of the first transistor; and an output circuit having an input coupled to the charge node, and an output for providing an output signal.
Claim 6
Dependent Claim
71 words
The circuit of claim 3 wherein the inverter means comprises: load means coupled to the first power supply terminal for dropping voltage in proportion to current passing therethrough; and a gain transistor having a first current electrode for providing the bias signal coupled to the load means and drawing current therethrough, a control electrode coupled to the charge node, and a second current electrode coupled to a second power supply terminal.
Claim 7
Dependent Claim
36 words
The circuit of claim 4, further comprising a resistive means, interposed between the second current electrode of the gain transistor and the second power supply terminal, for providing a voltage drop proportional to current passing therethrough.
Claim 8
Dependent Claim
22 words
The circuit of claim 5 further comprising a current means for providing current proportional to the bias signal to the resistive means.
Claim 9
Dependent Claim
34 words
The circuit of claim 3 wherein the first transistor is an enhancement-mode field effect transistor and the second transistor is an enhancement-mode field effect transistor having a threshold voltage of 0.0 to 0.4 volt.
Claim 10
Dependent Claim
60 words
The circuit of claim 7 wherein said output circuit comprises a third transistor having a control electrode coupled to the bias signal, a first current electrode coupled to the charge node, and a second current electrode coupled to an output terminal, wherein said third transistor is a enhancement-mode filed effect transistors having a threshold voltage of 0.0 to 0.4 volt.
Claim 11
Dependent Claim
93 words
The circuit of claim 8 wherein the inverter means comprises: a fourth transistor having a first current electrode coupled to the first power supply terminal, and a control electrode and a second current electrode coupled together, wherein said fourth transistor is a depletion-mode field effect transistor; and a fifth transistor having a first current electrode for providing the bias signal coupled to the control electrode and the second current electrode of the fourth transistor, a control electrode coupled to the charge node, and a second current electrode coupled to a second power supply.
Claim 12
Dependent Claim
60 words
The circuit of claim 9 further comprising a sixth transistor interposed between the second current electrode of the fifth transistor and the second power supply terminal, said sixth transistor having a control electrode and a first current electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the negative power supply terminal.
Claim 13
Dependent Claim
25 words
The circuit of claim 10 wherein the fifth and sixth transistors are enhancement-mode field effect transistors having a threshold voltage of 0.0 to 0.4 volt.
Claim 14
Dependent Claim
68 words
The circuit of claim 11 further comprising a seventh transistor having a control electrode coupled to the bias signal, a first current electrode coupled to the first power supply terminal, and a second current electrode coupled to the control electrode and the first current electrode of the sixth transistor, wherein said seventh transistor is an enhancement-mode field effect transistor having a threshold voltage of 0.0 to 0.4 volt.
Claim 15
Dependent Claim
36 words
The circuit of claim 12 further comprising an eighth transistor having a control electrode and a first current electrode coupled to the charge node, and a second current electrode coupled to the second power supply terminal.
Claim 16
Dependent Claim
36 words
The circuit of claim 13 further comprising a ninth transistor having a first current electrode coupled to the first power supply terminal, and a control electrode and a second current electrode coupled to the output terminal.
Claim 17
Dependent Claim
16 words
The circuit of claim 14 wherein the eighth and ninth transistors are depletion-mode field effect transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-10 | 1988-01-09 | 1988-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-10 | 1992-01-09 | 1992-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-10 | 1996-01-09 | 1996-07-10 | $7700.00 | Window Closed / Lapsed |