Sense circuit for use in variable threshold transistor memory arrays

Claim 1

A memory sense circuit for comparing the threshold voltage of a first and second variable threshold transistor wherein the source electrode of said first and second variable threshold transistors are coupled to a first voltage supply terminal and the gate electrodes are coupled to a first control signal terminal comprising: third, fourth and fifth field effect transistors each having a gate, source and drain electrode, the gate electrode of said third and fifth transistors coupled to a voltage source terminal, the source electrode of said third transistor coupled to the drain electrode of said first variable threshold transistor, the source electrode of said fifth transistor coupled to the drain electrode of said second variable threshold transistor, the drain electrode of said third transistor coupled to the gate electrode of said fourth transistor, the drain electrode of said fifth transistor coupled to the source electrode of said fourth transistor, means for applying a second control signal, and first means responsive to said second control signal for coupling the drain electrode of said third and fourth transistors to a return path of said first voltage supply terminal to precharge selected circuit nodes.