Stacked gate process flow for cross-point EPROM with internal access transistor

Claim 1

A method of fabricating a cross-point EPROM array in a silicon substrate of P-type conductivity, the array including a cell array area and a peripheral area, the method comprising: (a) forming a layer of first insulating material on the silicon substrate; (b) forming a first layer of polysilicon (poly 1) on the layer of insulating material; (c) forming a layer of second insulating material on the first layer of polysilicon; (d) forming a poly 1 mask to define parallel lines of the second insulating material and underlying first layer of polysilicon; (e) etching exposed portions of the second insulating material and underlying first layer of polysilicon to define parallel vertical strips of second insulating material and poly 1; (f) after removing the poly 1 mask, forming N+ regions in the silicon substrate between the parallel vertical strips of second insulating material and poly 1; (g) performing a differential oxidation step to form additional oxide on the second insulating material of the vertical strips while simultaneously forming oxide over the N+ regions; (h) forming a protect array mask for protecting the cell array area; (i) removing the second insulating material, and underlying poly 1 and first insulating material from the peripheral area; (j) after removing the protect array mask, forming gate oxide regions in the peripheral area; (k) forming a second layer of polysilicon (poly 2) over the structure formed in steps (a)-(j) above; (l) forming a layer of conductive material over the second layer of polysilicon; (m) forming a poly 2 mask on the layer of conductive material to define parallel lines of poly 2 that run perpendicular to the poly vertical strips; (n) etching the conductive material and the underlying poly 2 to define poly 2 word lines running perpendicular to the poly 1 strips but separated therefrom by the second insulating material. (o) forming a self aligned etch mask over the poly 2 mask in the peripheral area; (p) utilizing the poly 2 word lines in a stacked etch step to define the poly 1 floating gates at the cross-point EPROM cells of the array.

Claim 2

A method of fabricating a cross-point EPROM array in a silicon substrate of P-type conductivity, the array including a cell array area and a peripheral area, the method comprising: (a) forming a layer of first insulating material on the silicon substrate; (b) forming a first layer of polysilicon (poly 1) on the layer of insulating material; (c) forming a layer of second insulating material on the first layer of polysilicon; (d) forming a poly 1 mask to define parallel lines of the second insulating material and underlying first layer of polysilicon; (e) etching exposed portions of the second insulating material and underlying first layer of polysilicon to define parallel vertical strips of second insulating material and poly 1; (f) after removing the poly 1 mask, forming N+ regions in the silicon substrate between the parallel vertical strips of second insulating material and poly 1; (g) performing a differential oxidation step to form additional oxide on the second insulating material of the vertical strips while simultaneously forming oxide over the N+ regions; (h) forming a protect array mask for protecting the cell array area; (i) removing the second insulating material, and underlying poly 1 and first insulating material from the peripheral area; (j) after removing the protect array mask, forming gate oxide regions in the peripheral area; (k) forming a second layer of polysilicon (poly 2) over the structure formed in steps (a)-(j) above; (l) forming a layer of conductive material over the second layer of polysilicon; (m) forming a poly 2 mask on the layer of conductive material to define parallel lines of poly 2 that run perpendicular to the poly vertical strips; (n) etching the conductive material and the underlying poly 2 to define poly 2 word lines running perpendicular to the poly 1 strips but separated therefrom by the second insulating material. (o) forming a self aligned etch mask over the poly 2 mask in the peripheral area; (p) utilizing the poly 2 word lines in a stacked etch step to define the poly 1 floating gates at the cross-point EPROM cells of the array.

Claim 7

A method of fabricating a cross-point EPROM array in a silicon substrate of P-type conductivity, the EPROM array including a cell array area that includes a cell matrix comprising rows and columns of EPROM cells, the EPROM array further including a peripheral area that includes an access transistor area that includes access transistors, the EPROM cell columns being accessible via the access transistors the method comprising: (a) forming a layer of first insulating material on the silicon substrate; (b) forming a first layer of polysilicon (polyl) on the layer of insulating material; (c) forming a layer of second insulating material on the first layer of polysilicon; (d) forming a polyl mask to define parallel lines of the second insulating material and underlying first layer of polysilicon; (e) etching exposed portions of the second insulating material and underlying first layer of polysilicon to define parallel vertical strips of second insulating material and polyl; (f) after removing the polyl mask, forming N+ regions in the silicon substrate between the parallel vertical strips of second insulating material and polyl; (g) performing a differential oxidation step of form additional oxide on the second insulating material of the vertical strips while simultaneously forming oxide over the N+ region; (h) forming a protect array mask for protecting both the cell array area and the access transistor area of the peripheral area, the defining an unprotected area of the peripheral area; (i) removing the second insulating material, and underlying polyl and first insulating material from the unprotected area of the peripheral area; (j) after removing the protect array mask, such that parallel vertical lines of polyl still remain in the access transistor area, forming ate oxide regions in the peripheral area; (k) forming a thin layer of polysilicon over the structure formed in steps (a)-(j) above; (l) defining an access transistor gate mask to expose the access transistor area; (m) removing the second insulating material and thin polysilicon layer from the access transistor area; (n) forming a second layer of polysilicon (poly2) over the structure formal in steps (a)-(m) above; (o) forming a layer of conductive material over the second layer of polysilicon; (p) forming a poly2 mask on the layer of conductive material to define parallel lines of poly that non perpendicular to the polyl vertical strips; (q) etching the conductive material and the underlying poly2 to define poly2 and lines running perpendicular to the polyl strips but separated therefrom by the second insulating material; (r) forming a self-aligned etch mask over the poly2 mask in the peripheral area; and (s) utilizing the poly2 wordlines in a stacked etch step to define the polyl floating gates at the cross-point EPROM cells of the array.

Claim 8

A method of fabricating a cross-point EPROM array in a silicon substrate of P-type conductivity, the EPROM array including a cell array area that includes a cell matrix comprising rows and columns of EPROM cells, the EPROM array further including a peripheral area that includes an access transistor area that includes access transistors, the EPROM cell columns being accessible via the access transistors the method comprising: (a) forming a layer of first insulating material on the silicon substrate; (b) forming a first layer of polysilicon (polyl) on the layer of insulating material; (c) forming a layer of second insulating material on the first layer of polysilicon; (d) forming a polyl mask to define parallel lines of the second insulating material and underlying first layer of polysilicon; (e) etching exposed portions of the second insulating material and underlying first layer of polysilicon to define parallel vertical strips of second insulating material and polyl; (f) after removing the polyl mask, forming N+ regions in the silicon substrate between the parallel vertical strips of second insulating material and polyl; (g) performing a differential oxidation step of form additional oxide on the second insulating material of the vertical strips while simultaneously forming oxide over the N+ region; (h) forming a protect array mask for protecting both the cell array area and the access transistor area of the peripheral area, the defining an unprotected area of the peripheral area; (i) removing the second insulating material, and underlying polyl and first insulating material from the unprotected area of the peripheral area; (j) after removing the protect array mask, such that parallel vertical lines of polyl still remain in the access transistor area, forming ate oxide regions in the peripheral area; (k) forming a thin layer of polysilicon over the structure formed in steps (a)-(j) above; (l) defining an access transistor gate mask to expose the access transistor area; (m) removing the second insulating material and thin polysilicon layer from the access transistor area; (n) forming a second layer of polysilicon (poly2) over the structure formal in steps (a)-(m) above; (o) forming a layer of conductive material over the second layer of polysilicon; (p) forming a poly2 mask on the layer of conductive material to define parallel lines of poly that non perpendicular to the polyl vertical strips; (q) etching the conductive material and the underlying poly2 to define poly2 and lines running perpendicular to the polyl strips but separated therefrom by the second insulating material; (r) forming a self-aligned etch mask over the poly2 mask in the peripheral area; and (s) utilizing the poly2 wordlines in a stacked etch step to define the polyl floating gates at the cross-point EPROM cells of the array.