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US5234853A
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Method of producing a high voltage MOS transistor
Assignee: Fujitsu Ltd
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Filing: 1992-05-28
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Granted: 1993-08-10
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Expires: 2012-05-28
Abstract
Abstract A high voltage MOS transistor includes a semiconductor substrate (1) of a first semiconductor type, a gate electrode (14) formed on the semiconductor substrate via a gate oxide layer (13), first and second diffusion regions (15, 16) formed in the semiconductor substrate on both sides of the gate electrode and being of a second semiconductor type opposite to the first semiconductor type, and an electrode (38) which is directly connected to the first diffusion region (15) and is made up of a conductor layer (49) including polysilicon. An impurity concentration of the conductor layer (49) including the polysilicon is higher than an impurity concentration of the first diffusion region (15).
Inventors
- 👤 Shinichirou Ikemasu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D64/20; H10D64/23; H10D64/251; H10D64/60; H10D64/62; Y; Y10; Y10S; Y10S148/00; Y10S148/109
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
184 words
A method of producing a high voltage MOS transistor comprising the steps of: selectively forming a field oxide layer on a semiconductor substrate of a first semiconductor type; successively forming a gate oxide layer and a gate electrode on a region of the semiconductor substrate defined by the field oxide layer; forming first and second impurity regions of a second semiconductor type opposite to the first semiconductor type, in the semiconductor substrate on first and second sides of the gate electrode by a first ion implantation; covering the first impurity region with a mask layer; forming an additional mask layer on the mask layer; increasing an impurity concentration of the second impurity region to be higher than an impurity concentration of the first impurity region by a second ion implantation using the field oxide layer, the gate electrode, the additional mask layer and the mask layer as masks; and forming a conductor layer directly on at least the first impurity region so as to form an electrode, the conductor layer including polysilicon with an impurity concentration higher than that of the first impurity region.
Claim 2
Independent Claim
184 words
A method of producing a high voltage MOS transistor comprising the steps of: selectively forming a field oxide layer on a semiconductor substrate of a first semiconductor type; successively forming a gate oxide layer and a gate electrode on a region of the semiconductor substrate defined by the field oxide layer; forming first and second impurity regions of a second semiconductor type opposite to the first semiconductor type, in the semiconductor substrate on first and second sides of the gate electrode by a first ion implantation; covering the first impurity region with a mask layer; forming an additional mask layer on the mask layer; increasing an impurity concentration of the second impurity region to be higher than an impurity concentration of the first impurity region by a second ion implantation using the field oxide layer, the gate electrode, the additional mask layer and the mask layer as masks; and forming a conductor layer directly on at least the first impurity region so as to form an electrode, the conductor layer including polysilicon with an impurity concentration higher than that of the first impurity region.
Claim 3
Dependent Claim
70 words
The method of producing the high voltage MOS transistor as claimed in claim 1, wherein said step of forming the mask layer on the first impurity region includes: forming the mask layer on an entire surface of the semiconductor substrate; and selectively etching the mask layer so that a sidewall of the mask layer remains on a side surface of the gate electrode on at least the second impurity region.
Claim 4
Dependent Claim
45 words
The method of producing the high voltage MOS transistor as claimed in claim 2, wherein said step of forming the additional mask layer further includes: selectively etching the additional mask layer, so that side edge portions of the mask layer and the sidewall are smoothened.
Claim 5
Dependent Claim
22 words
The method of producing the high voltage MOS transistor as claimed in claim 1, wherein the conductor layer includes refractory metal silicide.
Claim 6
Dependent Claim
38 words
The method of producing the high voltage MOS transistor as claimed in claim 4, wherein the refractory metal silicide includes a refractory metal selected from a group consisting of tungsten (W), molybdenum (Mo), tantalum (Ta) and titanium (Ti).
Claim 7
Dependent Claim
104 words
The method of producing the high voltage MOS transistor as claimed in claim 1, wherein said step of forming the conductor layer includes: forming an insulator layer which covers the first and second impurity regions and the gate electrode; forming first and second contact holes in the insulator layer to respectively expose the first and second impurity regions, so that a first distance between the gate electrode and the first contact hole is greater than a second distance between the gate electrode and the second contact hole; and forming the conductor layer on the insulator layer to fill at least the first contact hole.
Claim 8
Dependent Claim
30 words
The method of producing the high voltage MOS transistor as claimed in claim 1, wherein the first semiconductor type is a p-type and the second semiconductor type is an n-type.
Claim 9
Independent Claim
223 words
A method of producing a semiconductor device having at least a high voltage MOS transistor and a memory cell including MOS transistor formed on a semiconductor substrate which is of a first semiconductor type, said method comprising the steps of: selectively forming a field oxide layer on the semiconductor substrate; successively forming gate oxide layers and gate electrodes on the semiconductor substrate in regions defined by the field oxide layer; forming impurity regions of a second semiconductor type opposite to the first semiconductor type in the semiconductor substrate on first and second sides of the gate electrodes by a first ion implantation; covering the impurity regions of the MOS transistor included in the memory cell and a first of the impurity regions of the high voltage MOS transistor by a mask layer; increasing an impurity concentration of a second of the impurity regions of the high voltage MOS transistor higher than an impurity concentration of the first impurity region by a second ion implantation using the field oxide layer, the gate electrode of the high voltage MOS transistor and the mask layer as masks; and forming a conductor layer directly on at least a part of the first impurity region so as to form an electrode, the conductor layer including polysilicon with an impurity concentration higher than that of the first impurity region.
Claim 10
Independent Claim
223 words
A method of producing a semiconductor device having at least a high voltage MOS transistor and a memory cell including MOS transistor formed on a semiconductor substrate which is of a first semiconductor type, said method comprising the steps of: selectively forming a field oxide layer on the semiconductor substrate; successively forming gate oxide layers and gate electrodes on the semiconductor substrate in regions defined by the field oxide layer; forming impurity regions of a second semiconductor type opposite to the first semiconductor type in the semiconductor substrate on first and second sides of the gate electrodes by a first ion implantation; covering the impurity regions of the MOS transistor included in the memory cell and a first of the impurity regions of the high voltage MOS transistor by a mask layer; increasing an impurity concentration of a second of the impurity regions of the high voltage MOS transistor higher than an impurity concentration of the first impurity region by a second ion implantation using the field oxide layer, the gate electrode of the high voltage MOS transistor and the mask layer as masks; and forming a conductor layer directly on at least a part of the first impurity region so as to form an electrode, the conductor layer including polysilicon with an impurity concentration higher than that of the first impurity region.
Claim 11
Dependent Claim
68 words
The method of producing the semiconductor device as claimed in claim 8, wherein said step of forming the mask layer on the first impurity region includes: forming the mask layer on an entire surface of the semiconductor substrate; and selectively etching the mask layer so that a sidewall of the mask layer remains on a side surface of the gate electrode on at least the second impurity region.
Claim 12
Dependent Claim
52 words
The method of producing the semiconductor device as claimed in claim 8, wherein said step of forming the mask layer further includes: forming an additional mask layer on the mask layer; and selectively etching the additional mask layer so that side edge portions of the mask layer and the sidewall are smoothened.
Claim 13
Dependent Claim
20 words
The method of producing the semiconductor device as claimed in claim 8, wherein the conductor layer includes refractory metal silicide.
Claim 14
Dependent Claim
36 words
The method of producing the semiconductor device as claimed in claim 11, wherein the refractory metal silicide includes a refractory metal selected from a group consisting of tungsten (W), molybdenum (Mo), tantalum (Ta) and titanium (Ti).
Claim 15
Dependent Claim
102 words
The method of producing the semiconductor device as claimed in claim 8, wherein said step of forming the conductor layer includes: forming an insulator layer which covers the first and second impurity regions and the gate electrode; forming first and second contact holes in the insulator layer to respectively expose the first and second impurity regions, so that a first distance between the gate electrode and the first contact hole is greater than a second distance between the gate electrode and the second contact hole; and forming the conductor layer on the insulator layer to fill at least the first contact hole.
Claim 16
Dependent Claim
28 words
The method of producing the semiconductor device as claimed in claim 8, wherein the first semiconductor type is a p-type and the second semiconductor type is an n-type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-09 | 1997-02-08 | 1997-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-09 | 2001-02-08 | 2001-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-09 | 2005-02-08 | 2005-08-10 | $7700.00 | Window Closed / Lapsed |