US5071784A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1990-11-21
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Granted: 1991-12-10
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Expires: 2010-11-21
Abstract
Abstract A semiconductor memory device includes a memory cell array comprised of a plurality of memory cells each having a single transfer transistor and a single capacitor and a peripheral circuit including a plurality of drive transistors and adapted to drive the memory cell. The source and drain regions of the transfer transistor have an impurity concentration lower in level than that of the source and drain regions of the drive transistor.
Inventors
- 👤 Yukio Takeuchi
- 👤 Satoshi Shinozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:27
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/01; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10P; H10P14/00; H10P14/40; H10P14/412; H10P32/00; H10P32/30; H10P32/302
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
282 words
A method of manufacturing a semiconductor memory device, comprising the steps of: preparing a semiconductor substrate to define a memory cell array forming area for a memory cell array and a peripheral circuit forming area for a peripheral circuit, the peripheral circuit being provided for driving the memory cell array; forming a plurality of memory cells in said memory cell array forming area and a peripheral circuit in said peripheral circuit forming area, each said memory cell including a single transfer transistor, comprised of source and drain regions and a gate, and a single capacitor, said peripheral circuit including at least one driver transistor comprised of source and drain regions and a gate, said source and drain regions of said transfer transistor and said driver transistor being doped to a low impurity concentration that precludes formation of a natural oxide film on surfaces of said source and drain regions; forming a masking film on said memory cell array forming area; doping impurities into said source and drain regions of said driver transistor of said peripheral circuit, said masking film blocking doping of the source and drain regions of said transfer transistors of said memory cell array; removing the mask film from said memory cell array forming area; forming a bit line of a polysilicon or a metal silicide having a high impurity concentration in contact with one of said source and drain regions of at least one of said transfer transistors; and diffusing from the bit line an impurity into a contact portion in said one of said source and drain regions of said at least one transfer transistor to form an ohmic contact between the contact portion and the bit line.
Claim 2
Independent Claim
282 words
A method of manufacturing a semiconductor memory device, comprising the steps of: preparing a semiconductor substrate to define a memory cell array forming area for a memory cell array and a peripheral circuit forming area for a peripheral circuit, the peripheral circuit being provided for driving the memory cell array; forming a plurality of memory cells in said memory cell array forming area and a peripheral circuit in said peripheral circuit forming area, each said memory cell including a single transfer transistor, comprised of source and drain regions and a gate, and a single capacitor, said peripheral circuit including at least one driver transistor comprised of source and drain regions and a gate, said source and drain regions of said transfer transistor and said driver transistor being doped to a low impurity concentration that precludes formation of a natural oxide film on surfaces of said source and drain regions; forming a masking film on said memory cell array forming area; doping impurities into said source and drain regions of said driver transistor of said peripheral circuit, said masking film blocking doping of the source and drain regions of said transfer transistors of said memory cell array; removing the mask film from said memory cell array forming area; forming a bit line of a polysilicon or a metal silicide having a high impurity concentration in contact with one of said source and drain regions of at least one of said transfer transistors; and diffusing from the bit line an impurity into a contact portion in said one of said source and drain regions of said at least one transfer transistor to form an ohmic contact between the contact portion and the bit line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-09 | 1995-06-10 | 1995-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-09 | 1999-06-10 | 1999-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-09 | 2003-06-10 | 2003-12-10 | $7700.00 | Window Closed / Lapsed |