Patent US5229635A successfully refreshed from Google Patents.
US5229635A
Expired / Lapsed
US
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ESD protection circuit and method for power-down application
Assignee: NXP BV
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Filing: 1991-08-21
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Granted: 1993-07-20
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Expires: 2011-08-21
Abstract
Abstract A technique for providing electrostatic discharge (ESD) protection for an open-drain CMOS I/O buffer circuit. having an output terminal. An NMOS enhancement-mode transistor has its drain connected to the VDD power bus for the buffer circuit, its source connected to the output terminal, and its gate connected to a noise-free internal VSS power bus (VSSI). The bulk region is connected to the VSS power bus (VSSE) for the I/O buffer circuit. ESD protection is provided by a parasitic lateral npn bipolar transistor that is inherent to the NMOS transistor. The parasitic lateral npn bipolar transistor has an emitter formed from the drain-to-bulk junction of the NMOS transistor, a collector formed from the source-to-bulk junction of the NMOS transistor, and a base formed in the bulk region.
Inventors
- 👤 Jeffrey M. Bessolo
- 👤 Gedaliahoo Krieger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:02
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
161 words
An independent electrostatic discharge (ESD) protection circuit for protection a CMOS I/O buffer circuit from electrostatic discharge (ESD) voltages between an I/O bonding pad and the VDD power bus for the I/O buffer circuit comprising: a separate NMOS enhancement-mode transistor structure providing a separate path for discharging ESD voltages between the I/O bonding pad and the VDD power bus said separate NMOS enhancement-mode transistor structure having the following connections: a drain terminal connected to a VDD power bus; a source terminal connected to the I/O bonding pad; a gate terminal connected to a VSS power bus; and a bulk region connected to the VSS power bus; and wherein said separate NMOS enhancement-mode transistor structure provides a separate parasitic lateral npn bipolar transistor for discharging ESD voltages between the I/O bonding pad and the VDD power bus, even when the CMOS I/O buffer circuit is powered down and when an external bus, to which the I/O bonding pad is connected, is active.
Claim 2
Dependent Claim
161 words
An independent electrostatic discharge (ESD) protection circuit for protection a CMOS I/O buffer circuit from electrostatic discharge (ESD) voltages between an I/O bonding pad and the VDD power bus for the I/O buffer circuit comprising: a separate NMOS enhancement-mode transistor structure providing a separate path for discharging ESD voltages between the I/O bonding pad and the VDD power bus said separate NMOS enhancement-mode transistor structure having the following connections: a drain terminal connected to a VDD power bus; a source terminal connected to the I/O bonding pad; a gate terminal connected to a VSS power bus; and a bulk region connected to the VSS power bus; and wherein said separate NMOS enhancement-mode transistor structure provides a separate parasitic lateral npn bipolar transistor for discharging ESD voltages between the I/O bonding pad and the VDD power bus, even when the CMOS I/O buffer circuit is powered down and when an external bus, to which the I/O bonding pad is connected, is active.
Claim 3
Dependent Claim
27 words
The ESD protection circuit of claim 1 wherein said CMOS I/O buffer transistor circuit has an open-drain output terminal, which is connected to the I/O bonding pad.
Claim 4
Dependent Claim
34 words
The ESD protection circuit of claim 1 wherein the NMOS enhancement-mode transistor structure is formed on a p-doped substrate and wherein the drain and the source are formed in n+ wells in said substrate.
Claim 5
Dependent Claim
47 words
The ESD protection circuit of claim 1 wherein the gate terminal of the NMOS enhancement-mode transistor structure is connected to a noise-free internal VSS power bus (VSSI) and the bulk region is connected to a VSS power bus for the output transistors driving the I/O buffer circuit.
References Cited (Backward Citations)
US4609931A
Cited
US4786956A
Cited
JPS61248549A
Cited
US4763184A
Cited
US4734752A
Cited
US4868705A
Cited
US4819047A
Cited
US4903093A
Cited
US4835416A
Cited
JPH01130554A
Cited
US4855620A
Cited
US4924339A
Cited
JPH01286354A
Cited
US4870530A
Cited
US5099302A
Cited
JPH02238668A
Cited
JPH02294063A
Cited
US5016078A
Cited
US5032742A
Cited
WO1991005371A1
Cited
US5028819A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-19 | 1997-01-18 | 1997-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-19 | 2001-01-18 | 2001-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-19 | 2005-01-18 | 2005-07-20 | $7700.00 | Window Closed / Lapsed |